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Implement a decode/issue FSM between fetch and execute
[soc.git] / src / soc / regfile /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
drwxr-xr-x - formal tree | history
-rw-r--r-- 13325 regfile.py blob | history | raw
-rw-r--r-- 6733 regfiles.py blob | history | raw
-rw-r--r-- 996 util.py blob | history | raw
-rw-r--r-- 6279 virtual_port.py blob | history | raw