.gitmodules

   1 [submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
   2         path = litex/soc/cores/cpu/lm32/verilog/submodule
   3         url = https://github.com/m-labs/lm32.git
   4 [submodule "litex/soc/cores/cpu/mor1kx/verilog"]
   5         path = litex/soc/cores/cpu/mor1kx/verilog
   6         url = https://github.com/openrisc/mor1kx.git
   7 [submodule "litex/soc/software/compiler_rt"]
   8         path = litex/soc/software/compiler_rt
   9         url = http://llvm.org/git/compiler-rt.git