litex.git
6 months agosoc/integration/csr_bridge: use registered version only when SDRAM is present. master
Florent Kermarrec [Fri, 14 Aug 2020 13:29:49 +0000 (15:29 +0200)]
soc/integration/csr_bridge: use registered version only when SDRAM is present.

Seems to be a good compromise for now.

6 months agointerconnect/wishbone/Wishbone2CSR: add registered version and use it as default.
Florent Kermarrec [Thu, 13 Aug 2020 22:47:05 +0000 (00:47 +0200)]
interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.

6 months agobuild/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environme...
Florent Kermarrec [Thu, 13 Aug 2020 22:10:38 +0000 (00:10 +0200)]
build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables).

http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522

6 months agocores/cpu/vexriscv_smp fix argument parsing
Dolu1990 [Thu, 13 Aug 2020 10:52:05 +0000 (12:52 +0200)]
cores/cpu/vexriscv_smp fix argument parsing

6 months agobios/main/sdram: fix speed reporting (Mbps/pin not MHz).
Florent Kermarrec [Tue, 11 Aug 2020 20:10:39 +0000 (22:10 +0200)]
bios/main/sdram: fix speed reporting (Mbps/pin not MHz).

6 months agoMerge pull request #627 from gsomlo/gls-dma-addr-64
enjoy-digital [Mon, 10 Aug 2020 19:44:02 +0000 (21:44 +0200)]
Merge pull request #627 from gsomlo/gls-dma-addr-64

RFC: cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address

6 months agocores/dma, liblitesdcard/sdcard: use 64 bits for dma base address
Gabriel Somlo [Mon, 6 Jul 2020 13:07:25 +0000 (09:07 -0400)]
cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address

Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).

Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
6 months agosoftware/bios: display SDRAM databits and freq.
Florent Kermarrec [Fri, 7 Aug 2020 17:49:02 +0000 (19:49 +0200)]
software/bios: display SDRAM databits and freq.

6 months agocpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.
Florent Kermarrec [Fri, 7 Aug 2020 12:47:21 +0000 (14:47 +0200)]
cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses.

LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.

6 months agocores/cpu: add external cpu_type.
Florent Kermarrec [Fri, 7 Aug 2020 09:15:12 +0000 (11:15 +0200)]
cores/cpu: add external cpu_type.

Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.

6 months agotargets: use platform.request_all on LedChaser.
Florent Kermarrec [Thu, 6 Aug 2020 18:02:17 +0000 (20:02 +0200)]
targets: use platform.request_all on LedChaser.

6 months agobuild/generic_platform: add request_all method.
Florent Kermarrec [Thu, 6 Aug 2020 18:00:07 +0000 (20:00 +0200)]
build/generic_platform: add request_all method.

6 months agocores/cpu/zynq7000: simplify using new loose parameter of Platform.request.
Florent Kermarrec [Thu, 6 Aug 2020 17:44:46 +0000 (19:44 +0200)]
cores/cpu/zynq7000: simplify using new loose parameter of Platform.request.

And avoid the try/except that can mask others errors.

6 months agoMerge pull request #624 from trabucayre/emio_zynq
enjoy-digital [Thu, 6 Aug 2020 17:34:03 +0000 (19:34 +0200)]
Merge pull request #624 from trabucayre/emio_zynq

soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode

6 months agobuild/generic_plaform: add loose parameter to return None when not available/existing.
Florent Kermarrec [Thu, 6 Aug 2020 17:32:02 +0000 (19:32 +0200)]
build/generic_plaform: add loose parameter to return None when not available/existing.

Similar to loose parameter already present on Platform.lookup_request.

6 months agoMerge pull request #625 from scanakci/blackparrot_litex
enjoy-digital [Thu, 6 Aug 2020 16:50:39 +0000 (18:50 +0200)]
Merge pull request #625 from scanakci/blackparrot_litex

Blackparrot human name change (IMA), minor transducer fix

6 months agointegration/soc/add_etherbone: pass phy to ethcore not self.ethphy.
Florent Kermarrec [Thu, 6 Aug 2020 16:22:42 +0000 (18:22 +0200)]
integration/soc/add_etherbone: pass phy to ethcore not self.ethphy.

Similar in most of the cases but added restrictions.

6 months agoupdate BlackParrot transducer
sadullah [Wed, 1 Jul 2020 03:01:25 +0000 (23:01 -0400)]
update BlackParrot transducer

6 months agoBlackparrot human name update
sadullah [Mon, 29 Jun 2020 19:33:43 +0000 (15:33 -0400)]
Blackparrot human name update

6 months agosoc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when...
Gwenhael Goavec-Merou [Thu, 6 Aug 2020 14:45:39 +0000 (16:45 +0200)]
soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode

6 months agoMerge pull request #623 from Dolu1990/vexriscv_smp
enjoy-digital [Thu, 6 Aug 2020 12:31:20 +0000 (14:31 +0200)]
Merge pull request #623 from Dolu1990/vexriscv_smp

cpu/vexriscv_smp Add --with-coherent-dma  --without-coherent-dma

6 months agocpu/vexriscv_smp Add --with-coherent-dma
Dolu1990 [Thu, 6 Aug 2020 11:32:48 +0000 (13:32 +0200)]
cpu/vexriscv_smp Add --with-coherent-dma

6 months agointegration/soc/add_sdram: update rules to connect main bus to dram.
Florent Kermarrec [Wed, 5 Aug 2020 16:01:12 +0000 (18:01 +0200)]
integration/soc/add_sdram: update rules to connect main bus to dram.

Requires connection when CPU does not have memory buses of when CPU has memory buses
but no DMA bus.

6 months agocpu/vexriscv_smp: fix args_read.
Florent Kermarrec [Wed, 5 Aug 2020 15:59:30 +0000 (17:59 +0200)]
cpu/vexriscv_smp: fix args_read.

6 months agocpu/vexriscv_smp: cleanup, fix coherent_dma connection.
Florent Kermarrec [Wed, 5 Aug 2020 15:25:13 +0000 (17:25 +0200)]
cpu/vexriscv_smp: cleanup, fix coherent_dma connection.

6 months agoMerge pull request #622 from antmicro/fix_connectors
enjoy-digital [Wed, 5 Aug 2020 10:30:34 +0000 (12:30 +0200)]
Merge pull request #622 from antmicro/fix_connectors

arty: Change USB-uart and I2S Pmod configuration

6 months agosoc/interconnect/axi: minor cleanups.
Florent Kermarrec [Wed, 5 Aug 2020 10:11:28 +0000 (12:11 +0200)]
soc/interconnect/axi: minor cleanups.

6 months agointerconnect/stream: set default AsyncFIFO depth to None and add depth parameter...
Florent Kermarrec [Wed, 5 Aug 2020 10:11:12 +0000 (12:11 +0200)]
interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.

6 months agoarty: Change USB-uart and I2S Pmod configuration
Pawel Sagan [Wed, 29 Jul 2020 19:14:40 +0000 (21:14 +0200)]
arty: Change USB-uart and I2S Pmod configuration

This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board).

6 months agointerconnect/csr: add CSR registers ordering support.
Florent Kermarrec [Wed, 5 Aug 2020 06:56:35 +0000 (08:56 +0200)]
interconnect/csr: add CSR registers ordering support.

The original CSR registers ordering (big: MSB on lower addresses) is not convenient
when the SoC is interfaced with a real OS (for example as a PCIe add-on board or
with a CPU running Linux).

With this, the original ordering is kept as default (big), but it can now be switched
to little to avoid software workarounds in drivers and should probably be in the future
the default for PCIe/Linux SoCs.

6 months agosoc/interconnect/csr: improve ident.
Florent Kermarrec [Wed, 5 Aug 2020 05:59:35 +0000 (07:59 +0200)]
soc/interconnect/csr: improve ident.

7 months agointegration/soc: add expection on decoder when full address space is mapped.
Florent Kermarrec [Tue, 4 Aug 2020 17:56:26 +0000 (19:56 +0200)]
integration/soc: add expection on decoder when full address space is mapped.

7 months agowishbone: revert default adr_width to 30.
Florent Kermarrec [Tue, 4 Aug 2020 17:55:46 +0000 (19:55 +0200)]
wishbone: revert default adr_width to 30.

7 months agotools/litex_json2dts: add missing copyrights.
Florent Kermarrec [Tue, 4 Aug 2020 14:38:02 +0000 (16:38 +0200)]
tools/litex_json2dts: add missing copyrights.

7 months agosetup: add litex_json2dts to console_scripts.
Florent Kermarrec [Tue, 4 Aug 2020 14:07:53 +0000 (16:07 +0200)]
setup: add litex_json2dts to console_scripts.

7 months agoMerge pull request #620 from antmicro/add_litex_json2dts
enjoy-digital [Tue, 4 Aug 2020 14:04:57 +0000 (16:04 +0200)]
Merge pull request #620 from antmicro/add_litex_json2dts

Add Linux DT generation script

7 months agobuild/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility...
Florent Kermarrec [Tue, 4 Aug 2020 13:37:56 +0000 (15:37 +0200)]
build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API.

7 months agobuild/sim: use json_object_get_int64 instead of json_object_get_uint64.
Florent Kermarrec [Tue, 4 Aug 2020 13:32:29 +0000 (15:32 +0200)]
build/sim: use json_object_get_int64 instead of json_object_get_uint64.

json_object_get_uint64 does not seem supported with old json-c versions.

7 months agoMerge pull request #619 from antmicro/jboc/sim-clocker
enjoy-digital [Tue, 4 Aug 2020 13:38:28 +0000 (15:38 +0200)]
Merge pull request #619 from antmicro/jboc/sim-clocker

Allow to define multiple simulation clocks

7 months agojson2dts: Add Linux DT generation script
Mateusz Holenko [Fri, 31 Jul 2020 12:42:05 +0000 (14:42 +0200)]
json2dts: Add Linux DT generation script

7 months agobuild/sim: improve timebase calculation (strict checks) and update modules
Jędrzej Boczar [Tue, 4 Aug 2020 12:00:58 +0000 (14:00 +0200)]
build/sim: improve timebase calculation (strict checks) and update modules

7 months agocores/uart: add txempty/rxfull CSRs.
Florent Kermarrec [Tue, 4 Aug 2020 11:49:50 +0000 (13:49 +0200)]
cores/uart: add txempty/rxfull CSRs.

Useful in some use cases, like flushing tx.

7 months agotools/litex_server: enable read_merger with CommUDP.
Florent Kermarrec [Tue, 4 Aug 2020 08:40:34 +0000 (10:40 +0200)]
tools/litex_server: enable read_merger with CommUDP.

Limited to 4 (current size of the buffer in liteeth.frontend.etherbone).

7 months agotest: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug...
Florent Kermarrec [Tue, 4 Aug 2020 07:37:53 +0000 (09:37 +0200)]
test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.

7 months agoMerge pull request #617 from gsomlo/gls_rocket_dma
enjoy-digital [Tue, 4 Aug 2020 07:38:58 +0000 (09:38 +0200)]
Merge pull request #617 from gsomlo/gls_rocket_dma

RFC: enable DMA with Rocket

7 months agodebug: make CI print offending values
Gabriel Somlo [Mon, 3 Aug 2020 20:59:39 +0000 (16:59 -0400)]
debug: make CI print offending values

7 months agoliblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz
Gabriel Somlo [Mon, 3 Aug 2020 16:03:39 +0000 (12:03 -0400)]
liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz

Rocket's DMA slave interface (and/or internal routing) currently
appears unable to route DMA writes from LiteSDCard at frequencies
above 25MHz (as tested on nexys4ddr, with Rocket, at 75MHz main
system clock frequency).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
7 months agocores/cpu/rocket: expose slave port for DMA
Gabriel Somlo [Wed, 29 Jul 2020 10:59:59 +0000 (06:59 -0400)]
cores/cpu/rocket: expose slave port for DMA

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
7 months agointegration/soc: make DMA slave region cover (at least) the lower 4GB
Gabriel Somlo [Mon, 3 Aug 2020 18:40:45 +0000 (14:40 -0400)]
integration/soc: make DMA slave region cover (at least) the lower 4GB

Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
7 months agointerconnect/wishbone: increase WB address width to 31
Gabriel Somlo [Mon, 3 Aug 2020 18:32:26 +0000 (14:32 -0400)]
interconnect/wishbone: increase WB address width to 31

This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
foo

7 months agosoc/interconnect/axi: add Wishbone2AXI converter
Gabriel Somlo [Sat, 1 Aug 2020 21:06:02 +0000 (17:06 -0400)]
soc/interconnect/axi: add Wishbone2AXI converter

7 months agocores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut.
Florent Kermarrec [Mon, 3 Aug 2020 16:47:17 +0000 (18:47 +0200)]
cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut.

7 months agobuild/sim: allow for arbitrary clocks generation using clockers
Jędrzej Boczar [Mon, 3 Aug 2020 14:52:54 +0000 (16:52 +0200)]
build/sim: allow for arbitrary clocks generation using clockers

7 months agobuild/sim: use a real timebase in the simulation
Jędrzej Boczar [Mon, 3 Aug 2020 13:21:24 +0000 (15:21 +0200)]
build/sim: use a real timebase in the simulation

7 months agoMerge pull request #615 from pepijndevos/openfpgaloader
enjoy-digital [Mon, 3 Aug 2020 12:01:50 +0000 (14:01 +0200)]
Merge pull request #615 from pepijndevos/openfpgaloader

Add openFPGALoader programmer

7 months agoremove debugging
Pepijn de Vos [Sat, 1 Aug 2020 09:06:08 +0000 (11:06 +0200)]
remove debugging

7 months agoadd openFPGAloader programmer
Pepijn de Vos [Sat, 1 Aug 2020 09:05:09 +0000 (11:05 +0200)]
add openFPGAloader programmer

7 months agocpu/vexriscv/core: use variant name as human_name.
Florent Kermarrec [Fri, 31 Jul 2020 06:59:53 +0000 (08:59 +0200)]
cpu/vexriscv/core: use variant name as human_name.

Allow it to be shown in the BIOS and help support.

7 months agocpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with...
Florent Kermarrec [Fri, 31 Jul 2020 06:58:30 +0000 (08:58 +0200)]
cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache.

7 months agocpu/zynq7000: set csr map to 0x00000000.
Florent Kermarrec [Thu, 30 Jul 2020 19:37:25 +0000 (21:37 +0200)]
cpu/zynq7000: set csr map to 0x00000000.

7 months agoMerge pull request #611 from antmicro/jboc/axi-lite
enjoy-digital [Thu, 30 Jul 2020 12:22:21 +0000 (14:22 +0200)]
Merge pull request #611 from antmicro/jboc/axi-lite

soc/interconnect/axi: add AXILite -> AXI converter

7 months agotools/litex_server/read_merger: review/simplify a bit.
Florent Kermarrec [Thu, 30 Jul 2020 11:58:40 +0000 (13:58 +0200)]
tools/litex_server/read_merger: review/simplify a bit.

7 months agoMerge pull request #605 from cklarhorst/feature-uart-read-merger
enjoy-digital [Thu, 30 Jul 2020 11:56:48 +0000 (13:56 +0200)]
Merge pull request #605 from cklarhorst/feature-uart-read-merger

Merge sequential reads for the UART litex_server backend

7 months agosoc/interconnect/axi: add AXILite -> AXI converter
Jędrzej Boczar [Thu, 30 Jul 2020 11:38:17 +0000 (13:38 +0200)]
soc/interconnect/axi: add AXILite -> AXI converter

7 months agocpu/blackparrot: minor cleanups, add sim variant (since use different flist).
Florent Kermarrec [Thu, 30 Jul 2020 10:10:32 +0000 (12:10 +0200)]
cpu/blackparrot: minor cleanups, add sim variant (since use different flist).

7 months agoMerge pull request #610 from Dolu1990/vexriscv_smp
enjoy-digital [Wed, 29 Jul 2020 16:11:00 +0000 (18:11 +0200)]
Merge pull request #610 from Dolu1990/vexriscv_smp

soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth

7 months agosoc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth
Dolu1990 [Wed, 29 Jul 2020 10:40:16 +0000 (12:40 +0200)]
soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth

7 months agoMerge branch 'master' into vexriscv_smp
Dolu1990 [Wed, 29 Jul 2020 09:14:09 +0000 (11:14 +0200)]
Merge branch 'master' into vexriscv_smp

7 months agointegration/soc/add_sdram: allow the CPU to add the direct memory buses when adding...
Florent Kermarrec [Wed, 29 Jul 2020 09:10:05 +0000 (11:10 +0200)]
integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram.

This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.

7 months agocores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus...
Florent Kermarrec [Wed, 29 Jul 2020 07:34:07 +0000 (09:34 +0200)]
cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing.

Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to
the DMA bus of Rocket when the direct memory bus is used.

7 months agoMerge branch 'master' into vexriscv_smp
Dolu1990 [Tue, 28 Jul 2020 17:11:54 +0000 (19:11 +0200)]
Merge branch 'master' into vexriscv_smp

7 months agosoc/cores/cpu/vexriscv_smp config update
Dolu1990 [Tue, 28 Jul 2020 17:07:02 +0000 (19:07 +0200)]
soc/cores/cpu/vexriscv_smp config update

7 months agoCHANGES: update.
Florent Kermarrec [Tue, 28 Jul 2020 16:37:23 +0000 (18:37 +0200)]
CHANGES: update.

7 months agocpu/vexriscv_smp: move litedram import, remove os.path import.
Florent Kermarrec [Tue, 28 Jul 2020 16:10:32 +0000 (18:10 +0200)]
cpu/vexriscv_smp: move litedram import, remove os.path import.

7 months agolitex_setup: fix vexriscv-smp repository.
Florent Kermarrec [Tue, 28 Jul 2020 14:56:32 +0000 (16:56 +0200)]
litex_setup: fix vexriscv-smp repository.

7 months agoMerge pull request #607 from Dolu1990/vexriscv_smp
enjoy-digital [Tue, 28 Jul 2020 14:53:55 +0000 (16:53 +0200)]
Merge pull request #607 from Dolu1990/vexriscv_smp

soc/cores/cpu/vexriscv_smp integration

7 months agosoc/cores/cpu/vexriscv_smp integration
Dolu1990 [Tue, 28 Jul 2020 14:20:16 +0000 (16:20 +0200)]
soc/cores/cpu/vexriscv_smp integration

7 months agoliblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.
Florent Kermarrec [Tue, 28 Jul 2020 12:36:49 +0000 (14:36 +0200)]
liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz.

7 months agointegration/soc/etherbone: expose ethcore (useful to combine udp/etherbone).
Florent Kermarrec [Mon, 27 Jul 2020 17:57:29 +0000 (19:57 +0200)]
integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone).

7 months agointegration/soc: fix dma_bus typo.
Florent Kermarrec [Mon, 27 Jul 2020 09:06:09 +0000 (11:06 +0200)]
integration/soc: fix dma_bus typo.

7 months agoMerge sequential reads for the UART litex_server backend
Christian Klarhorst [Sun, 26 Jul 2020 11:19:32 +0000 (13:19 +0200)]
Merge sequential reads for the UART litex_server backend

The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).

Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
 18s (with this merge function)

The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.

7 months agotargets: keep in sync with litex-boards.
Florent Kermarrec [Fri, 24 Jul 2020 14:34:17 +0000 (16:34 +0200)]
targets: keep in sync with litex-boards.

7 months agoMerge pull request #604 from antmicro/jboc/axi-lite
enjoy-digital [Fri, 24 Jul 2020 12:54:11 +0000 (14:54 +0200)]
Merge pull request #604 from antmicro/jboc/axi-lite

Improve AXI Lite data width converters

7 months agosoc/interconnect/axi: add basic AXI Lite up-converter
Jędrzej Boczar [Fri, 24 Jul 2020 11:46:51 +0000 (13:46 +0200)]
soc/interconnect/axi: add basic AXI Lite up-converter

7 months agoMerge pull request #603 from enjoy-digital/socdoc-extensions
Sean Cross [Fri, 24 Jul 2020 08:42:23 +0000 (16:42 +0800)]
Merge pull request #603 from enjoy-digital/socdoc-extensions

Socdoc extensions

7 months agodoc: socdoc: document new `sphinx_extra_config` parameter
Sean Cross [Fri, 24 Jul 2020 08:03:24 +0000 (16:03 +0800)]
doc: socdoc: document new `sphinx_extra_config` parameter

This allows for appending additional configuration to `conf.py`.

Signed-off-by: Sean Cross <sean@xobs.io>
7 months agoMerge pull request #602 from enjoy-digital/socdoc-extensions
enjoy-digital [Fri, 24 Jul 2020 08:02:06 +0000 (10:02 +0200)]
Merge pull request #602 from enjoy-digital/socdoc-extensions

doc: socdoc: document `sphinx_extensions` parameter

7 months agolitex: add `sphinx_extra_config` to `generate_docs()`
Sean Cross [Fri, 24 Jul 2020 08:01:54 +0000 (16:01 +0800)]
litex: add `sphinx_extra_config` to `generate_docs()`

This allows us to append additional strings to the sphinx `conf.py`.

Signed-off-by: Sean Cross <sean@xobs.io>
7 months agodoc: socdoc: document `sphinx_extensions` parameter
Sean Cross [Fri, 24 Jul 2020 07:47:59 +0000 (15:47 +0800)]
doc: socdoc: document `sphinx_extensions` parameter

This adds documentation for `sphinx_extensions` which can be used to add
additional features to output.

Signed-off-by: Sean Cross <sean@xobs.io>
7 months agosoc/interconnect/axi: separate AXI Lite converter channels
Jędrzej Boczar [Thu, 23 Jul 2020 14:54:02 +0000 (16:54 +0200)]
soc/interconnect/axi: separate AXI Lite converter channels

7 months agoCHANGES: update.
Florent Kermarrec [Thu, 23 Jul 2020 16:02:58 +0000 (18:02 +0200)]
CHANGES: update.

7 months agocore/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.
Florent Kermarrec [Thu, 23 Jul 2020 15:40:46 +0000 (17:40 +0200)]
core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq.

This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.

An example is available on litex-boards.

7 months agoliblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial...
Florent Kermarrec [Wed, 22 Jul 2020 21:15:36 +0000 (23:15 +0200)]
liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency).

7 months agoCHANGES: update.
Florent Kermarrec [Wed, 22 Jul 2020 21:10:26 +0000 (23:10 +0200)]
CHANGES: update.

7 months agoMerge pull request #600 from antmicro/jboc/axi-lite
enjoy-digital [Wed, 22 Jul 2020 21:03:07 +0000 (23:03 +0200)]
Merge pull request #600 from antmicro/jboc/axi-lite

Implement AXI Lite interconnect

7 months agosoc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency).
Florent Kermarrec [Wed, 22 Jul 2020 16:43:28 +0000 (18:43 +0200)]
soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency).

When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.

This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.

7 months agotest/axi: move all AXI Lite tests to separate file
Jędrzej Boczar [Wed, 22 Jul 2020 14:59:17 +0000 (16:59 +0200)]
test/axi: move all AXI Lite tests to separate file

7 months agosoc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
Jędrzej Boczar [Wed, 22 Jul 2020 14:57:51 +0000 (16:57 +0200)]
soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"

7 months agotest/axi: add crossbar stress tests
Jędrzej Boczar [Wed, 22 Jul 2020 14:31:51 +0000 (16:31 +0200)]
test/axi: add crossbar stress tests

7 months agosoc/integration: add bus standard parser arguments
Jędrzej Boczar [Wed, 22 Jul 2020 13:55:49 +0000 (15:55 +0200)]
soc/integration: add bus standard parser arguments