1 [> 2020.XX, planned for July 2020
2 ---------------------------------
6 - Fix flush_cpu_icache on VexRiscv.
10 - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
11 - Improve WishboneBridge.
12 - Improve Diamond constraints.
13 - Add LedChaser on boards.
14 - Speedup Memtest using an LFSR.
15 - Add Microwatt CPU support.
16 - Improve boards's programmers.
17 - BIOS history, autocomplete.
19 - Add nMigen dependency.
20 - Properly integrate Minerva CPU.
22 [> API changes/Deprecation
23 --------------------------
24 - Add --build --load arguments to targets.
27 [> 2020.04, released April 28th, 2020
28 -------------------------------------
32 First release of LiteX and the ecosystem of cores!
34 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
35 Cores/SoCs (with or without CPU).
37 The common components of a SoC are provided directly:
38 - Buses and Streams (Wishbone, AXI, Avalon-ST)
40 - Common cores (RAM, ROM, Timer, UART, etc...)
41 - CPU wrappers/integration
43 And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
44 PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
46 It also provides build backends for open-source and vendors toolchains.
56 [> API changes/Deprecation
57 --------------------------
58 - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.