1 [> 2020.XX, planned for July 2020
2 ---------------------------------
6 - Fix flush_cpu_icache on VexRiscv.
10 - BIOS history, autocomplete.
12 - Add nMigen dependency.
13 - Properly integrate Minerva CPU.
15 [> API changes/Deprecation
16 --------------------------
20 [> 2020.04, released April 28th, 2020
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25 First release of LiteX and the ecosystem of cores!
27 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
28 Cores/SoCs (with or without CPU).
30 The common components of a SoC are provided directly:
31 - Buses and Streams (Wishbone, AXI, Avalon-ST)
33 - Common cores (RAM, ROM, Timer, UART, etc...)
34 - CPU wrappers/integration
36 And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
37 PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
39 It also provides build backends for open-source and vendors toolchains.
49 [> API changes/Deprecation
50 --------------------------
51 - https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.