soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found...
[litex.git] / MANIFEST.in
1 graft litex/build/sim
2 graft litex/soc/software
3 graft litex/soc/cores/cpu/lm32/verilog
4 graft litex/soc/cores/cpu/mor1kx/verilog
5 graft litex/soc/cores/cpu/picorv32/verilog