targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll

[litex.git] / MANIFEST.in

graft litex/build/sim
graft litex/soc/software
graft litex/soc/cores/cpu/lm32/verilog
graft litex/soc/cores/cpu/mor1kx/verilog
graft litex/soc/cores/cpu/picorv32/verilog