Makefile

   1 CFLAGS=-O3 -Wall
   2 CXXFLAGS=-g -g
   3
   4 YOSYS     ?= yosys
   5 NEXTPNR   ?= nextpnr-ecp5
   6 ECPPACK   ?= ecppack
   7 OPENOCD   ?= openocd
   8
   9 all = ls2_verilator
  10
  11 all: $(all)
  12
  13 uart_files = $(wildcard ../uart16550/rtl/verilog/*.v)
  14
  15 # Verilator sim
  16 VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
  17 ifeq (, $(VERILATOR_ROOT))
  18 $(soc_dram_tbs):
  19         $(error "Verilator is required to make this target !")
  20 else
  21
  22 VERILATOR_CFLAGS=-O3
  23 VERILATOR_FLAGS=-O3
  24
  25 endif
  26
  27 # Hello world
  28 MEMORY_SIZE=8192
  29 RAM_INIT_FILE=hello_world/hello_world.bin
  30 RAM_INIT_FILE=coldboot/coldboot.bin
  31 SIM_MAIN_BRAM=false
  32
  33 # Micropython
  34 #MEMORY_SIZE=393216
  35 #RAM_INIT_FILE=micropython/firmware.bin
  36
  37 # Linux
  38 #MEMORY_SIZE=536870912
  39 #RAM_INIT_FILE=dtbImage.microwatt.bin
  40 #SIM_MAIN_BRAM=false
  41 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
  42
  43 FPGA_TARGET ?= verilator
  44
  45 ifeq ($(FPGA_TARGET), verilator)
  46 RESET_LOW=true
  47 CLK_INPUT=50000000
  48 CLK_FREQUENCY=50000000
  49 clkgen=fpga/clk_gen_bypass.vhd
  50 endif
  51
  52 ls2.v: src/ls2.py
  53         python3 src/ls2.py sim $(RAM_INIT_FILE)
  54
  55 # Need to investigate why yosys is hitting verilator warnings,
  56 # and eventually turn on -Wall
  57 microwatt-verilator: ls2.v \
  58                      verilator/microwatt-verilator.cpp \
  59                      verilator/uart-verilator.c
  60         verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
  61     --assert \
  62         --top-module top \
  63     --cc ls2.v \
  64     --cc external_core_top.v \
  65     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \
  66     -o $@ -I../uart16550/rtl/verilog \
  67         -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \
  68             -Wno-BLKANDNBLK \
  69             -Wno-COMBDLY  \
  70             -Wno-CASEINCOMPLETE \
  71             -Wno-WIDTH \
  72          --savable \
  73          --trace \
  74         #    --unroll-count 256 \
  75         #    --output-split 5000 \
  76         #    --output-split-cfuncs 500 \
  77         #    --output-split-ctrace 500 \
  78         make -C obj_dir -f Vtop.mk
  79         @cp -f obj_dir/microwatt-verilator microwatt-verilator
  80
  81 clean:
  82         rm -fr obj_dir microwatt-verilator ls2.v
  83
  84 .PHONY: all clean