README

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   5
   6             Copyright 2007-2015 / M-Labs Ltd
   7             Copyright 2012-2015 / Enjoy-Digital
   8
   9     a high performance and small footprint SoC based on Migen
  10
  11 [> Features
  12 -----------
  13  * LatticeMico32 CPU, modified to include an optional MMU (experimental).
  14  * mor1kx (a better OpenRISC implementation) as alternative CPU option.
  15  * High performance memory controller capable of issuing several SDRAM commands
  16    per FPGA cycle.
  17  * Supports SDR, DDR, LPDDR, DDR2 and DDR3.
  18  * Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI
  19    flash controller, Ethernet MAC, and more.
  20  * High performance:
  21    - on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
  22    SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
  23    - on Kintex-7, 125MHz system clock frequencies (up to 200MHz without DDR3),
  24    64Gbps DDR3 SDRAM bandwidth.
  25  * Low resource usage: basic implementation fits easily in Spartan-6 LX9.
  26  * Portable and easy to customize thanks to Python- and Migen-based
  27    architecture.
  28  * Design new peripherals using Migen and benefit from automatic CSR maps
  29    and logic, etc.
  30  * Possibility to encapsulate legacy Verilog/VHDL code.
  31  * Complex FPGA cores that can be used integrated in MiSoC or in standalone:
  32      - LiteEth:   a small footprint and configurable Ethernet core
  33      - LiteSATA:  a small footprint and configurable SATA core
  34      - LiteScope: a small footprint and configurable logic analyzer core
  35
  36 MiSoC comes with built-in support for the following boards:
  37  * Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
  38  * Milkymist One, the original M-Labs video synthesizer [XC6SLX45]
  39  * Papilio Pro, a simple and low-cost development board [XC6SLX9]
  40  * Pipistrello, a simple board with USB and HDMI [XC6SLX45]
  41  * De0 Nano, a simple and low-cost development board [CYCLONEIV]
  42  * KC705, a Kintex-7 devboard from Xilinx [XC7K325T]
  43 MiSoC is portable and support for other boards can easily be added as external
  44 modules.
  45
  46 [> Quick start guide
  47 --------------------
  48 0. If cloned from Git without the --recursive option, get the submodules:
  49   git submodule update --init
  50
  51 1. Install Python 3.3+, Migen and FPGA vendor's development tools.
  52   Get Migen from: https://github.com/m-labs/migen
  53
  54 2. Install JTAG tools.
  55   For Mixxeo and M1:          http://urjtag.org
  56   For Papilio Pro and KC705:  http://xc3sprog.sourceforge.net
  57   For De0 Nano:               USBBlaster from Altera
  58   We recommend using xc3sprog for Xilinx devices, but Vivado programmer
  59   is also supported for Xilinx 7-series.
  60
  61 3. (Optional, only needed if you want to flash the bistream/software)
  62   Obtain and build any required flash proxy bitstreams. Flash proxy bitstreams
  63   give JTAG access to a flash chip through the FPGA.
  64   For Mixxeo and M1: https://github.com/m-labs/fjmem-m1
  65   For Papilio Pro:   https://github.com/GadgetFactory/Papilio-Loader
  66     (xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit)
  67   For KC705: https://github.com/m-labs/bscan_spi_kc705
  68
  69 4. Compile and install binutils. Take the latest version from GNU.
  70   mkdir build && cd build
  71   ../configure --target=lm32-elf
  72   make
  73   make install
  74
  75 5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  76   (version 4.5 or >=4.9).
  77   rm -rf libstdc++-v3
  78   mkdir build && cd build
  79   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
  80     --disable-libssp
  81   make
  82   make install
  83
  84 6. Build and flash the BIOS and bitstream. Run from MiSoC:
  85   For Mixxeo:      ./make.py all
  86   For M1:          ./make.py -p m1 all
  87   For Papilio Pro: ./make.py -t ppro all
  88   For Pipistrello: ./make.py -t pipistrello all
  89   For De0 Nano:    ./make.py -t de0nano all load-bitstream
  90   For KC705:       ./make.py -t kc705 all
  91
  92   If just want to load the bitstream in volatile SRAM use:
  93     all load-bitstream
  94
  95 7. Run a terminal program on the board's serial port at 115200 8-N-1.
  96   You should get the BIOS prompt.
  97
  98 8. Read and experiment with the source!
  99   Come to our IRC channel and mailing list!
 100   A simple target is provided to test MiSoC easily with your board:
 101     Create your target with a clock and serial pins.
 102     Build and test it: ./make.py -t simple -p your_platform all load-bitstream
 103   If you don't have access to a FPGA board, you can also try MiSoC
 104   with Verilator:
 105     Download and install Verilator: http://www.veripool.org/
 106     Test it: ./make.py -t simple -p sim build-bitstream
 107
 108 9. Contribute a patch!
 109   Once you have experimented with stuff, please send your results back.
 110   For more details on how to do so, you can see the CONTRIBUTING.md file.
 111
 112 [> License
 113 ----------
 114 MiSoC is released under the very permissive two-clause BSD license. Under
 115 the terms of this license, you are authorized to use MiSoC for
 116 closed-source proprietary designs.
 117 Even though we do not require you to do so, those things are awesome, so please
 118 do them if possible:
 119  * tell us that you are using MiSoC
 120  * cite MiSoC in publications related to research it has helped
 121  * send us feedback and suggestions for improvements
 122  * send us bug reports when something goes wrong
 123  * send us the modifications and improvements you have done to MiSoC.
 124    The use of "git format-patch" is recommended. If your submission is large
 125    and complex and/or you are not sure how to proceed, feel free to discuss it
 126    on the mailing list or IRC (#m-labs on Freenode) beforehand.
 127
 128 See LICENSE file for full copyright and license info.
 129
 130 [> Links
 131 --------
 132 Web:
 133   http://m-labs.hk
 134   http://enjoy-digital.fr
 135
 136 Code repository:
 137   https://github.com/m-labs/misoc
 138
 139 You can contact us on the public mailing list devel [AT] lists.m-labs.hk.