2 / / (_) /____ / __/ /_/ /
3 / /__/ / __/ -_) _// __/ _ \
4 /____/_/\__/\__/___/\__/_//_/
6 Copyright 2012-2015 / EnjoyDigital
7 florent@enjoy-digital.fr
9 A small footprint and configurable Ethernet core
10 developed by EnjoyDigital
14 HTML : www.enjoy-digital.fr/litex/liteeth/
15 PDF : www.enjoy-digital.fr/litex/liteeth.pdf
19 LiteEth provides a small footprint and configurable Ethernet core.
21 LiteEth is part of LiteX libraries whose aims are to lower entry level of
22 complex FPGA IP cores by providing simple, elegant and efficient implementations
23 ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
25 The core uses simple and specific streaming buses and will provides in the future
26 adapters to use standardized AXI or Avalon-ST streaming buses.
28 Since Python is used to describe the HDL, the core is highly and easily
31 LiteEth uses technologies developed in partnership with M-Labs Ltd:
32 - Migen enables generating HDL with Python in an efficient way.
33 - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
35 LiteEth can be used as a Migen/MiSoC library (by simply installing it
36 with the provided setup.py) or can be integrated with your standard design flow
37 by generating the verilog rtl that you will use as a standard core.
41 - Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
42 - Hardware UDP/IP stack with ARP and ICMP
44 [> Possibles improvements
45 -------------------------
46 - add standardized interfaces (AXI, Avalon-ST)
47 - add DMA interface to MAC
48 - add hardware Etherbone support
49 - add RGMII/SGMII PHYs
50 - ... See below Support and Consulting :)
52 If you want to support these features, please contact us at florent [AT]
53 enjoy-digital.fr. You can also contact our partner on the public mailing list
54 devel [AT] lists.m-labs.hk.
59 1. Install Python3 and Xilinx's Vivado software
61 2. Obtain Migen and install it:
62 (we use EnjoyDigital fork for now until new features are merged
64 git clone https://github.com/enjoy-digital/migen
66 python3 setup.py install
69 3. Obtain LiteScope and install it:
70 git clone https://github.com/enjoy-digital/litescope
72 python3 setup.py install
76 git clone https://github.com/m-labs/misoc --recursive
77 XXX add setup.py to MiSoC for external use of misoclib?
80 git clone https://github.com/enjoy-digital/liteeth
82 6. Build and load UDP loopback design (only for KC705 for now):
83 python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
85 7. Test design (only for KC705 for now):
86 go to ./test directory and run:
87 change com port in config.py to your com port
88 try to ping 192.168.1.40
92 Simulations are available in ./liteth/test/:
99 All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
100 To run a simulation, move to ./liteeth/test and run:
104 An UDP loopback is provided and be controlled with: /test/test_udp.py
108 LiteEth is released under the very permissive two-clause BSD license. Under
109 the terms of this license, you are authorized to use LiteEth for closed-source
111 Even though we do not require you to do so, those things are awesome, so please
113 - tell us that you are using LiteEth
114 - cite LiteEth in publications related to research it has helped
115 - send us feedback and suggestions for improvements
116 - send us bug reports when something goes wrong
117 - send us the modifications and improvements you have done to LiteEth.
119 [> Support and Consulting
120 --------------------------
121 We love open-source hardware and like sharing our designs with others.
123 LiteEth is developed and maintained by EnjoyDigital.
125 If you would like to know more about LiteEth or if you are already a happy
126 user and would like to extend it for your needs, EnjoyDigital can provide standard
127 commercial support as well as consulting services.
129 So feel free to contact us, we'd love to work with you! (and eventually shorten
130 the list of the possible improvements :)
133 E-mail: florent [AT] enjoy-digital.fr