README

   1                        __   _ __      _  __
   2                       / /  (_) /____ | |/_/
   3                      / /__/ / __/ -_)>  <
   4                     /____/_/\__/\__/_/|_|
   5                          Migen inside
   6
   7                 Build your hardware, easily!
   8              Copyright 2012-2015 Enjoy-Digital
   9
  10 [> Intro
  11 ---------
  12 LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
  13 our cores, integrate them in complete SoC and load/flash them to the hardware.
  14
  15 The structure of LiteX is kept close to MiSoC to ease collaboration between
  16 projects and efforts are made to keep cores developed with LiteX compatible
  17 with MiSoC (user will only need to import new modules introduced by LiteX).
  18
  19 LiteX is based on Migen.
  20
  21 [> License
  22 -----------
  23 LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
  24 Since it is based on MiSoC, please also refer to LICENSE file in soc directory
  25 or git history to get correct copyrights.
  26
  27 [> Sub-packages
  28 ----------------
  29 gen:
  30   Provides specific or experimentatl modules to generate HDL that are not integrated
  31   in Migen.
  32
  33 build:
  34   Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  35   simulate HDL code or full SoCs.
  36
  37 soc:
  38   Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  39   to build a SoC from such cores.
  40
  41 boards:
  42   Provides platforms and targets for the supported boards.
  43
  44 [> Quick start guide
  45 --------------------
  46 0. If cloned from Git without the --recursive option, get the submodules:
  47   git submodule update --init
  48
  49 1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
  50   Get Migen from: https://github.com/m-labs/migen
  51
  52 2. Compile and install binutils. Take the latest version from GNU.
  53   mkdir build && cd build
  54   ../configure --target=lm32-elf
  55   make
  56   make install
  57
  58 3. (Optional, only if you want to use a lm32 CPU in you SoC)
  59   Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  60   (version 4.5 or >=4.9).
  61   rm -rf libstdc++-v3
  62   mkdir build && cd build
  63   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
  64     --disable-libssp
  65   make
  66   make install
  67
  68 4. Build the target of your board...:
  69   Go to boards/targets and execute the target you want to build
  70
  71 5. ... and/or install Verilator and test LiteX on your computer:
  72   Download and install Verilator: http://www.veripool.org/
  73   Go to boards/targets
  74   ./sim.py
  75
  76 6. Run a terminal program on the board's serial port at 115200 8-N-1.
  77   You should get the BIOS prompt.
  78
  79 [> Contact
  80 E-mail: florent [AT] enjoy-digital.fr