README

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   5
   6             Copyright 2007-2015 / M-Labs Ltd
   7             Copyright 2012-2015 / Enjoy-Digital
   8
   9     a high performance and small footprint SoC based on Migen
  10
  11 [> Features
  12 -----------
  13  * LatticeMico32 CPU, modified to include an optional MMU (experimental).
  14  * mor1kx (a better OpenRISC implementation) as alternative CPU option.
  15  * High performance memory controller capable of issuing several SDRAM commands
  16    per FPGA cycle.
  17  * Supports SDR, DDR, LPDDR, DDR2 and DDR3.
  18  * Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI
  19    flash controller, Ethernet MAC, and more.
  20  * High performance:
  21    - on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
  22    SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
  23    - on Kintex-7, 125MHz system clock frequencies (up to 200MHz without DDR3),
  24    64Gbps DDR3 SDRAM bandwidth.
  25  * Low resource usage: basic implementation fits easily in Spartan-6 LX9.
  26  * Portable and easy to customize thanks to Python- and Migen-based
  27    architecture.
  28  * Design new peripherals using Migen and benefit from automatic CSR maps
  29    and logic, etc.
  30  * Possibility to encapsulate legacy Verilog/VHDL code.
  31  * Complex FPGA cores that can be used integrated in MiSoC or standalone:
  32      - LiteEth:   a small footprint and configurable Ethernet core
  33
  34 MiSoC comes with built-in support for the following boards:
  35  * Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
  36  * Milkymist One, the original M-Labs video synthesizer [XC6SLX45]
  37  * Papilio Pro, a simple and low-cost development board [XC6SLX9]
  38  * Pipistrello, a simple board with USB and HDMI [XC6SLX45]
  39  * De0 Nano, a simple and low-cost development board [CYCLONEIV]
  40  * KC705, a Kintex-7 devboard from Xilinx [XC7K325T]
  41  * Versa, a low-cost Lattice development board [ECP3-35]
  42 MiSoC is portable and support for other boards can easily be added as external
  43 modules.
  44
  45 [> Quick start guide
  46 --------------------
  47 0. If cloned from Git without the --recursive option, get the submodules:
  48   git submodule update --init
  49
  50 1. Install Python 3.3+, Migen and FPGA vendor's development tools.
  51   Get Migen from: https://github.com/m-labs/migen
  52
  53 2. Install JTAG tools.
  54   For Mixxeo and M1:          http://urjtag.org
  55   For Papilio Pro and KC705:  http://xc3sprog.sourceforge.net
  56   For De0 Nano:               USBBlaster from Altera
  57   We recommend using xc3sprog for Xilinx devices, but Vivado programmer
  58   is also supported for Xilinx 7-series.
  59
  60 3. (Optional, only needed if you want to flash the bistream/software)
  61   Obtain and build any required flash proxy bitstreams. Flash proxy bitstreams
  62   give JTAG access to a flash chip through the FPGA.
  63   For Mixxeo and M1: https://github.com/m-labs/fjmem-m1
  64   For Papilio Pro:   https://github.com/GadgetFactory/Papilio-Loader
  65     (xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit)
  66   For KC705: https://github.com/m-labs/bscan_spi_kc705
  67
  68 4. Compile and install binutils. Take the latest version from GNU.
  69   mkdir build && cd build
  70   ../configure --target=lm32-elf
  71   make
  72   make install
  73
  74 5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  75   (version 4.5 or >=4.9).
  76   rm -rf libstdc++-v3
  77   mkdir build && cd build
  78   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
  79     --disable-libssp
  80   make
  81   make install
  82
  83 6. Build and flash the BIOS and bitstream. Run from MiSoC:
  84   For Mixxeo:      ./make.py all
  85   For M1:          ./make.py -p m1 all
  86   For Papilio Pro: ./make.py -t ppro all
  87   For Pipistrello: ./make.py -t pipistrello all
  88   For De0 Nano:    ./make.py -t de0nano all load-bitstream
  89   For KC705:       ./make.py -t kc705 all
  90
  91   If just want to load the bitstream in volatile SRAM use:
  92     all load-bitstream
  93
  94 7. Run a terminal program on the board's serial port at 115200 8-N-1.
  95   You should get the BIOS prompt.
  96
  97 8. Read and experiment with the source!
  98   Come to our IRC channel and mailing list!
  99   A simple target is provided to test MiSoC easily with your board:
 100     Create your target with a clock and serial pins.
 101     Build and test it: ./make.py -t simple -p your_platform all load-bitstream
 102   If you don't have access to a FPGA board, you can also try MiSoC
 103   with Verilator:
 104     Download and install Verilator: http://www.veripool.org/
 105     Test it: ./make.py -t simple -p sim build-bitstream
 106
 107 9. Contribute a patch!
 108   Once you have experimented with stuff, please send your results back.
 109   For more details on how to do so, you can see the CONTRIBUTING.md file.
 110
 111 [> License
 112 ----------
 113 MiSoC is released under the very permissive two-clause BSD license. Under
 114 the terms of this license, you are authorized to use MiSoC for
 115 closed-source proprietary designs.
 116 Even though we do not require you to do so, those things are awesome, so please
 117 do them if possible:
 118  * tell us that you are using MiSoC
 119  * cite MiSoC in publications related to research it has helped
 120  * send us feedback and suggestions for improvements
 121  * send us bug reports when something goes wrong
 122  * send us the modifications and improvements you have done to MiSoC.
 123    The use of "git format-patch" is recommended. If your submission is large
 124    and complex and/or you are not sure how to proceed, feel free to discuss it
 125    on the mailing list or IRC (#m-labs on Freenode) beforehand.
 126
 127 See LICENSE file for full copyright and license info.
 128
 129 [> Links
 130 --------
 131 Web:
 132   http://m-labs.hk
 133   http://enjoy-digital.fr
 134
 135 Code repository:
 136   https://github.com/m-labs/misoc
 137
 138 You can contact us on the public mailing list devel [AT] lists.m-labs.hk.