README

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   5
   6                 Copyright 2014-2015 HKU
   7
   8         A small footprint and configurable SATA core
   9        developed for HKU by M-Labs Ltd & EnjoyDigital
  10
  11 [> Intro
  12 ---------
  13 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
  14
  15 LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
  16 FPGA IP cores by providing simple, elegant and efficient implementations of
  17 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
  18
  19 The core uses simple and specific streaming buses and will provides in the future
  20 adapters to use standardized AXI or Avalon-ST streaming buses.
  21
  22 Since Python is used to describe the HDL, the core is highly and easily
  23 configurable.
  24
  25 The synthetizable BIST can be used as a starting point to integrate SATA in
  26 your own SoC.
  27
  28 LiteSATA uses technologies developed in partnership with M-Labs Ltd:
  29  - Migen enables generating HDL with Python in an efficient way.
  30  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
  31
  32 LiteSATA can be used as a Migen/MiSoC library (by simply installing  it
  33 with the provided setup.py) or can be integrated with your standard design flow
  34 by generating the verilog rtl that you will use as a standard core.
  35
  36 [> Features
  37 -----------
  38 PHY:
  39   - OOB, COMWAKE, COMINIT
  40   - ALIGN inserter/remover and bytes alignment on K28.5
  41   - 8B/10B encoding/decoding in transceiver
  42   - Errors detection and reporting
  43   - 32 bits interface
  44   - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
  45 Core:
  46   Link:
  47     - CONT inserter/remover
  48     - Scrambling/Descrambling of data
  49     - CRC inserter/checker
  50     - HOLD insertion/detection
  51     - Errors detection and reporting
  52   Transport/Command:
  53     - Easy to use user interfaces (Can be used with or without CPU)
  54     - 48 bits sector addressing
  55     - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
  56     - Errors detection and reporting
  57
  58 Frontend:
  59   - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
  60   - Ports arbitration transparent to the user
  61   - Synthetizable BIST
  62
  63 [> Possibles improvements
  64 -------------------------
  65 - add standardized interfaces (AXI, Avalon-ST)
  66 - add NCQ support
  67 - add AES hardware encryption
  68 - add on-the-flow compression/decompression
  69 - add support for Altera PHYs.
  70 - add support for Lattice PHYs.
  71 - add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
  72   supported)
  73 - add Zynq Linux drivers.
  74 - ... See below Support and Consulting :)
  75
  76 If you want to support these features, please contact us at florent [AT]
  77 enjoy-digital.fr. You can also contact our partner on the public mailing list
  78 devel [AT] lists.m-labs.hk.
  79
  80 [> Getting started
  81 ------------------
  82 1. Install Python3 and Xilinx's Vivado software
  83
  84 2. Obtain Migen and install it:
  85   git clone https://github.com/m-labs/migen
  86   cd migen
  87   python3 setup.py install
  88   cd ..
  89
  90 3. Obtain LiteScope and install it:
  91   git clone https://github.com/m-labs/litescope
  92   cd litescope
  93   python3 setup.py install
  94   cd ..
  95
  96 4. Obtain MiSoC:
  97   git clone https://github.com/m-labs/misoc --recursive
  98   XXX add setup.py to MiSoC for external use of misoclib?
  99
 100 5. Obtain LiteSATA
 101   git clone https://github.com/enjoy-digital/litesata
 102
 103 6. Build and load BIST design (only for KC705 for now):
 104   python3 make.py all
 105
 106 7. Test design (only for KC705 for now):
 107   go to ./test directory and run:
 108   python3 bist.py
 109
 110 8. If you only want to build the core and use it with your
 111   regular design flow:
 112   python3 make.py -t core build-core
 113
 114 [> Simulations:
 115   Simulations are available in ./lib/sata/test:
 116     - crc_tb
 117     - scrambler_tb
 118     - phy_datapath_tb
 119     - link_tb
 120     - command_tb
 121     - bist_tb
 122   hdd.py is a simplified HDD model implementing all SATA layers.
 123   To run a simulation, move to ./lib/sata/test and run:
 124     make simulation_name
 125
 126 [> Tests :
 127   A synthetizable BIST is provided and can be controlled with ./test/bist.py
 128   By using Miscope and the provided ./test/test_link.py example you are able to
 129   visualize the internal logic of the design and even inject the captured data in
 130   the HDD model!
 131
 132 [> License
 133 -----------
 134 LiteSATA is released under the very permissive two-clause BSD license. Under the
 135 terms of this license, you are authorized to use LiteSATA for closed-source
 136 proprietary designs.
 137 Even though we do not require you to do so, those things are awesome, so please
 138 do them if possible:
 139  - tell us that you are using LiteSATA
 140  - cite LiteSATA in publications related to research it has helped
 141  - send us feedback and suggestions for improvements
 142  - send us bug reports when something goes wrong
 143  - send us the modifications and improvements you have done to LiteSATA.
 144
 145 [> Support and Consulting
 146 --------------------------
 147 We love open-source hardware and like sharing our designs with others.
 148
 149 LiteSATA is developed and maintained by EnjoyDigital.
 150
 151 If you would like to know more about LiteSATA or if you are already a happy user
 152 and would like to extend it for your needs, EnjoyDigital can provide standard
 153 commercial support as well as consulting services.
 154
 155 So feel free to contact us, we'd love to work with you! (and eventually shorten
 156 the list of the possible improvements :)
 157
 158 [> Contact
 159 E-mail: florent [AT] enjoy-digital.fr