README

   1 [> migScope
   2 ------------
   3
   4 This is a small Logic Analyser to be embedded in a Fpga design to debug internal
   5 or external signals.
   6
   7 [> Status:
   8 Early development phase
   9
  10 Simulation:
  11 -tb_spi2Csr      :   Test Spi <--> Csr Bridge : [Ok]
  12 -tb_TriggerCsr   :   Test Trigger with Csr    : [Ok]
  13 -tb_RecorderCsr  :   Test Recorder with Csr   : [Ok]
  14 -tb_MigScope     :   Global Test with Csr     : [Ok]
  15
  16 Example Design:
  17 -de0_nano        :   Generate Signals in FPGA and probe them with migScope : [Wip]
  18                      Toolchain [Ok]
  19 -de1             :   Generate Signals in FPGA and probe them with migScope : [Wip]
  20                      Toolchain [Ok]
  21                      - test_MigIo : Led & Switch Test controlled by Python [Ok]
  22                      - test_MigLa : Logic Analyzer controlled by Python [Wip]
  23                                     (Still some glitches in received Data, let's use
  24                                      migScope to debug itself :))
  25
  26 [> Contact
  27 E-mail: florent@enjoy-digital.fr