1 ![LiteX](doc/litex.png)
3 Copyright 2012-2020 / EnjoyDigital
5 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
6 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
8 LiteX is a FPGA design/SoC builder that can be used to build cores, create
9 SoCs and full FPGA designs.
11 LiteX is based on Migen/MiSoC and provides specific building/debugging tools
12 for a higher level of abstraction and compatibily with the LiteX core ecosystem.
14 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
15 SoC builder to create/develop/debug FPGA SoCs in Python.
17 # Typical LiteX design flow:
26 +-------+ | | Your design
27 | LiteX +---> ready to be used!
29 +----------------------+ | |
30 |LiteX Cores Ecosystem +--> |
31 +----------------------+ +-^-------^-+
32 (Eth, SATA, DRAM, USB, | |
33 PCIe, Video, etc...) + +
37 LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
38 and is compatible with the LiteX's Cores Ecosystem:
40 | Name | Build Status | Description |
41 | ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
42 | [LiteDRAM](http://github.com/enjoy-digital/litedram) | [![](https://travis-ci.org/enjoy-digital/litedram.svg?branch=master)](https://travis-ci.org/enjoy-digital/litedram) | DRAM |
43 | [LiteEth](http://github.com/enjoy-digital/liteeth) | [![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth) | Ethernet |
44 | [LitePCIe](http://github.com/enjoy-digital/litepcie) | [![](https://travis-ci.com/enjoy-digital/litepcie.svg?branch=master)](https://travis-ci.com/enjoy-digital/litepcie) | PCIe |
45 | [LiteSATA](http://github.com/enjoy-digital/litesata) | [![](https://travis-ci.com/enjoy-digital/litesata.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesata) | SATA |
46 | [LiteSDCard](http://github.com/enjoy-digital/litesdcard) | [![](https://travis-ci.com/enjoy-digital/litesdcard.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesdcard) | SD card |
47 | [LiteICLink](http://github.com/enjoy-digital/liteiclink) | [![](https://travis-ci.com/enjoy-digital/liteiclink.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteiclink) | Inter-Chip communication |
48 | [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [![](https://travis-ci.com/enjoy-digital/litejesd204b.svg?branch=master)](https://travis-ci.com/enjoy-digital/litejesd204b) | JESD204B |
49 | [LiteVideo](http://github.com/enjoy-digital/litevideo) | [![](https://travis-ci.com/enjoy-digital/litevideo.svg?branch=master)](https://travis-ci.com/enjoy-digital/litevideo) | VGA, DVI, HDMI |
50 | [LiteScope](http://github.com/enjoy-digital/litescope) | [![](https://travis-ci.com/enjoy-digital/litescope.svg?branch=master)](https://travis-ci.com/enjoy-digital/litescope) | Logic analyzer |
54 Provides specific or experimental modules to generate HDL that are not integrated in Migen.
57 Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
60 Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
63 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
65 # Papers, Presentations, Tutorials, Links
66 **FPGA lessons/tutorials:**
67 - https://github.com/enjoy-digital/fpga_101
69 **OSDA paper/slides:**
70 - https://osda.gitlab.io/19/1.1.pdf
71 - https://osda.gitlab.io/19/1.1-slides.pdf
73 **Linux on LiteX-Vexriscv:**
74 - https://github.com/litex-hub/linux-on-litex-vexriscv
76 **RISC-V Getting Started Guide:**
77 - https://risc-v-getting-started-guide.readthedocs.io/en/latest/
79 **LiteX vs. Vivado First Impressions:**
80 - https://www.bunniestudios.com/blog/?p=5018
82 **35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
83 - https://www.youtube.com/watch?v=AlmVxR0417c
85 **Tim has to many projects - LatchUp Edition:**
86 https://www.youtube.com/watch?v=v7WrTmexod0
88 # Very Quick start guide (for newcomers)
89 TimVideos.us has done an awesome job for setting up a LiteX environment easily in the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
91 It's recommended for newcomers to go this way. Various FPGA boards are supported and multiple examples provided! You can even run Linux on your FPGA using LiteX very easily!
93 Migen documentation can be found here: https://m-labs.hk/migen/manual
95 # Quick start guide (for advanced users)
96 0. Install Python 3.5+ and FPGA vendor's development tools.
97 1. Install Migen/LiteX and the LiteX's cores:
99 On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
102 $ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
103 $ chmod +x litex_setup.py
104 $ ./litex_setup.py init install --user (--user to install to user directory)
106 Later, if you need to update all repositories:
108 $ ./litex_setup.py update
110 3. Install a RISC-V toolchain:
114 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
115 $ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
116 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
120 $ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
121 $ tar -xvf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
122 $ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin/bin/
124 4. Build the target of your board...:
125 Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
127 5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX on your computer
131 $ sudo dnf install libevent-devel json-c-devel
135 $ sudo apt install libevent-dev libjson-c-dev verilator
142 $ brew install json-c verilator libevent
143 $ brew cask install tuntap
147 6. Run a terminal program on the board's serial port at 115200 8-N-1.
149 You should get the BIOS prompt like the one below.
151 ![bios_screenshot](doc/bios_screenshot.png)
154 E-mail: florent@enjoy-digital.fr