build.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4
   5 from mibuild.platforms import m1
   6 from mibuild.tools import write_to_file
   7
   8 import top
   9 import cif
  10
  11 def main():
  12         platform = m1.Platform()
  13         soc = top.SoC(platform)
  14
  15         platform.add_platform_command("""
  16 NET "{clk50}" TNM_NET = "GRPclk50";
  17 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
  18 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
  19 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
  20
  21 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
  22
  23 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
  24 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
  25 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
  26 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
  27 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
  28 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
  29
  30 NET "asfifo*/counter_read/gray_count*" TIG;
  31 NET "asfifo*/counter_write/gray_count*" TIG;
  32 NET "asfifo*/preset_empty*" TIG;
  33
  34 NET "{dviclk0}" TNM_NET = "GRPdviclk0";
  35 NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
  36 TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
  37 NET "{dviclk1}" TNM_NET = "GRPdviclk1";
  38 NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
  39 TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
  40 """,
  41                 clk50=platform.lookup_request("clk50"),
  42                 phy_rx_clk=platform.lookup_request("eth_clocks").rx,
  43                 phy_tx_clk=platform.lookup_request("eth_clocks").tx,
  44                 dviclk0=platform.lookup_request("dvi_in", 0).clk,
  45                 dviclk1=platform.lookup_request("dvi_in", 1).clk)
  46
  47         for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
  48                 platform.add_source_dir(os.path.join("verilog", d))
  49         platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
  50                 "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
  51                 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
  52                 "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
  53                 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
  54                 "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
  55                 "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
  56         platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
  57
  58         platform.build_cmdline(soc)
  59         csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
  60         write_to_file("software/include/hw/csr.h", csr_header)
  61
  62 if __name__ == "__main__":
  63         main()