build.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 from mibuild.platforms import m1
   5 import top
   6
   7 def main():
   8         plat = m1.Platform()
   9         soc = top.SoC()
  10
  11         # set pin constraints
  12         plat.request("clk50", obj=soc.crg.clk50_pad)
  13         plat.request("user_btn", 1, obj=soc.crg.trigger_reset)
  14         plat.request("norflash_rst_n", obj=soc.crg.norflash_rst_n)
  15         plat.request("vga_clock", obj=soc.crg.vga_clk_pad)
  16         plat.request("ddram_clock", obj=soc.crg, name_map=lambda s: "ddr_clk_pad_" + s)
  17         plat.request("eth_clocks", obj=soc.crg, name_map=lambda s: "eth_" + s + "_clk_pad")
  18
  19         plat.request("norflash", obj=soc.norflash)
  20         plat.request("serial", obj=soc.uart)
  21         plat.request("ddram", obj=soc.ddrphy, name_map=lambda s: "sd_" + s)
  22         plat.request("eth", obj=soc.minimac, name_map=lambda s: "phy_" + s)
  23         plat.request("vga", obj=soc.fb, name_map=lambda s: "vga_" + s)
  24         plat.request("dvi_in", 0, obj=soc.dvisampler0)
  25         plat.request("dvi_in", 1, obj=soc.dvisampler1)
  26
  27         # set extra constraints
  28         plat.add_platform_command("""
  29 NET "{clk50}" TNM_NET = "GRPclk50";
  30 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
  31 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
  32 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
  33
  34 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
  35
  36 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
  37 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
  38 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
  39 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
  40 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
  41 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
  42
  43 NET "asfifo*/counter_read/gray_count*" TIG;
  44 NET "asfifo*/counter_write/gray_count*" TIG;
  45 NET "asfifo*/preset_empty*" TIG;
  46 """,
  47                 clk50=soc.crg.clk50_pad,
  48                 phy_rx_clk=soc.crg.eth_rx_clk_pad,
  49                 phy_tx_clk=soc.crg.eth_tx_clk_pad)
  50
  51         # add Verilog sources
  52         for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
  53                 plat.add_source_dir(os.path.join("verilog", d))
  54         plat.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
  55                 "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
  56                 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
  57                 "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
  58                 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
  59                 "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
  60                 "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
  61         plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
  62
  63         plat.build_cmdline(soc)
  64
  65 if __name__ == "__main__":
  66         main()