4 # list Verilog sources before changing directory
7 root
= os
.path
.join("verilog", d
)
8 files
= os
.listdir(root
)
11 verilog_sources
.append(os
.path
.join(root
, f
))
12 def add_core_files(d
, files
):
14 verilog_sources
.append(os
.path
.join("verilog", d
, f
))
16 add_core_dir("s6ddrphy")
17 add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
18 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
19 "lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
20 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
21 "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
22 "jtag_tap_spartan6.v"])
26 def str2file(filename
, contents
):
27 f
= open(filename
, "w")
32 (src_verilog
, src_ucf
) = top
.get()
33 str2file("soc.v", src_verilog
)
34 str2file("soc.ucf", src_ucf
)
35 verilog_sources
.append("build/soc.v")
37 # generate XST project file
39 for s
in verilog_sources
:
40 xst_prj
+= "verilog work ../" + s
+ "\n"
41 str2file("soc.prj", xst_prj
)