4 # list Verilog sources before changing directory
7 for root
, subFolders
, files
in os
.walk(os
.path
.join("verilog", d
)):
9 verilog_sources
.append(os
.path
.join(root
, f
))
10 def add_core_files(d
, files
):
12 verilog_sources
.append(os
.path
.join("verilog", d
, f
))
13 add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
14 "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
15 "lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
16 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
17 "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
18 "jtag_tap_spartan6.v"])
21 os
.system("rm -rf build/*")
24 def str2file(filename
, contents
):
25 f
= open(filename
, 'w')
30 (src_verilog
, src_ucf
) = top
.Get()
31 str2file("soc.v", src_verilog
)
32 str2file("soc.ucf", src_ucf
)
33 verilog_sources
.append("build/soc.v")
37 for s
in verilog_sources
:
38 xst_prj
+= "verilog work ../" + s
+ "\n"
39 str2file("soc.prj", xst_prj
)
40 str2file("soc.xst", """run
47 -reduce_control_sets auto
49 -p xc6slx45-fgg484-2""")
50 os
.system("xst -ifn soc.xst")
53 os
.system("ngdbuild -uc soc.ucf soc.ngc")
56 os
.system("map -ol high -w soc.ngd")
59 os
.system("par -ol high -w soc.ncd soc-routed.ncd")
62 os
.system("bitgen -g LCK_cycle:6 -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")