5 #include "microwatt_soc.h"
14 static inline uint32_t read32(const void *addr
)
16 return *(volatile uint32_t *)addr
;
19 static inline void write32(void *addr
, uint32_t value
)
21 *(volatile uint32_t *)addr
= value
;
31 uint32_t zero0
; // reserved
32 uint32_t zero1
; // reserved
38 void memcpy(void *dest
, void *src
, size_t n
) {
40 //cast src and dest to char*
41 char *src_char
= (char *)src
;
42 char *dest_char
= (char *)dest
;
44 dest_char
[i
] = src_char
[i
]; //copy contents byte by byte
47 void uart_writeuint32(uint32_t val
) {
48 const char lut
[] = { '0', '1', '2', '3', '4', '5', '6', '7',
49 '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
50 uint8_t *val_arr
= (uint8_t*)(&val
);
53 for (i
= 0; i
< 4; i
++) {
54 putchar(lut
[(val_arr
[3-i
] >> 4) & 0xF]);
55 putchar(lut
[val_arr
[3-i
] & 0xF]);
63 static bool fl_read(void *dst
, uint32_t offset
, uint32_t size
)
66 memcpy(d
, (void *)(unsigned long)(SPI_FLASH_BASE
+ offset
), size
);
70 static unsigned long copy_flash(unsigned int offset
)
74 unsigned int i
, poff
, size
, off
;
77 puts("Trying flash...\r\n");
78 if (!fl_read(&ehdr
, offset
, sizeof(ehdr
)))
80 if (!IS_ELF(ehdr
) || ehdr
.e_ident
[EI_CLASS
] != ELFCLASS64
) {
81 puts("Doesn't look like an elf64\r\n");
84 if (ehdr
.e_ident
[EI_DATA
] != ELFDATA2LSB
||
85 ehdr
.e_machine
!= EM_PPC64
) {
86 puts("Not a ppc64le binary\r\n");
90 poff
= offset
+ ehdr
.e_phoff
;
91 for (i
= 0; i
< ehdr
.e_phnum
; i
++) {
92 if (!fl_read(&ph
, poff
, sizeof(ph
)))
94 if (ph
.p_type
!= PT_LOAD
)
97 /* XXX Add bound checking ! */
99 addr
= (void *)ph
.p_vaddr
;
100 off
= offset
+ ph
.p_offset
;
101 //printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
102 puts("Copy segment ");
105 uart_writeuint32(size
);
107 uart_writeuint32((uint32_t)addr
);
109 fl_read(addr
, off
, size
);
110 poff
+= ehdr
.e_phentsize
;
113 puts("Booting from DRAM at");
114 uart_writeuint32((unsigned int)ehdr
.e_entry
);
115 //flush_cpu_icache();
119 for (i
= 0; i
< 8; i
++) {
120 uart_writeuint32(ehdr
.e_ident
[i
]);
129 // Defining gram_[read|write] allows a trace of all register
130 // accesses to be dumped to console for debugging purposes.
131 // To use, define GRAM_RW_FUNC in gram.h
132 uint32_t gram_read(const struct gramCtx
*ctx
, void *addr
) {
136 uart_writeuint32((unsigned long)addr
);
137 dword
= readl((unsigned long)addr
);
139 uart_writeuint32((unsigned long)dword
);
145 int gram_write(const struct gramCtx
*ctx
, void *addr
, uint32_t value
) {
146 puts("gram_write: ");
147 uart_writeuint32((unsigned long)addr
);
149 uart_writeuint32((unsigned long)value
);
150 writel(value
, (unsigned long)addr
);
157 const int kNumIterations
= 14;
158 int res
, failcnt
= 0;
160 unsigned long ftr
, spi_offs
=0x0;
161 volatile uint32_t *ram
= (uint32_t*)MEMORY_BASE
;
164 //puts("Firmware launched...\n");
167 puts(" Soc signature: ");
168 tmp
= readl(SYSCON_BASE
+ SYS_REG_SIGNATURE
);
169 uart_writeuint32(tmp
);
170 puts(" Soc features: ");
171 ftr
= readl(SYSCON_BASE
+ SYS_REG_INFO
);
172 if (ftr
& SYS_REG_INFO_HAS_UART
)
174 if (ftr
& SYS_REG_INFO_HAS_DRAM
)
176 if (ftr
& SYS_REG_INFO_HAS_BRAM
)
178 if (ftr
& SYS_REG_INFO_HAS_SPI_FLASH
)
180 if (ftr
& SYS_REG_INFO_HAS_LITEETH
)
184 if (ftr
& SYS_REG_INFO_HAS_SPI_FLASH
) {
185 puts("SPI Offset: ");
186 spi_offs
= readl(SYSCON_BASE
+ SYS_REG_SPI_INFO
);
187 uart_writeuint32(spi_offs
);
195 // print out configuration parameters for QSPI
196 volatile uint32_t *qspi_cfg
= (uint32_t*)0xc0003000;
197 for (int k
=0; k
< 2; k
++) {
198 tmp
= readl((unsigned long)&(qspi_cfg
[k
]));
200 //uart_writeuint32(k);
202 //uart_writeuint32(tmp);
206 volatile uint32_t *qspi
= (uint32_t*)spi_mem
;
207 volatile uint8_t *qspi_bytes
= (uint8_t*)spi_mem
;
208 // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
209 // tmp = readl((unsigned long)&(qspi[0]));
210 for (i
=0;i
<1000;i
++) {
211 tmp
= readl((unsigned long)&(qspi
[i
]));
212 uart_writeuint32(tmp
);
217 for (i
=0;i
<1000;i
++) {
218 tmp
= readb((unsigned long)&(qspi_bytes
[i
]));
219 uart_writeuint32(tmp
);
225 tmp
= readl((unsigned long)&(qspi
[0x1000/4]));
227 uart_writeuint32(tmp
);
232 unsigned char c
= getchar();
234 if (c
== 13) { // if CR send LF
237 tmp
= readl((unsigned long)&(qspi
[1<<i
]));
239 uart_writeuint32(1<<i
);
241 uart_writeuint32(tmp
);
250 volatile uint32_t *hyperram
= (uint32_t*)0xa0000000;
251 writel(0xDEAF0123, (unsigned long)&(hyperram
[0]));
252 tmp
= readl((unsigned long)&(hyperram
[0]));
254 unsigned char c
= getchar();
256 if (c
== 13) { // if CR send LF
259 writel(0xDEAF0123+i
, (unsigned long)&(hyperram
[1<<i
]));
260 tmp
= readl((unsigned long)&(hyperram
[1<<i
]));
262 uart_writeuint32(1<<i
);
264 uart_writeuint32(tmp
);
273 for (int persistence
=0; persistence
< 1000; persistence
++) {
274 puts("DRAM init... ");
278 struct gramProfile profile
= {
280 0xb20, 0x806, 0x200, 0x0
287 struct gramProfile profile
= {
289 0x0320, 0x0006, 0x0200, 0x0000
295 struct gramProfile profile2
;
296 gram_init(&ctx
, &profile
, (void*)MEMORY_BASE
,
297 (void*)DRAM_CTRL_BASE
,
298 (void*)DRAM_INIT_BASE
);
301 puts("MR profile: ");
302 uart_writeuint32(profile
.mode_registers
[0]);
304 uart_writeuint32(profile
.mode_registers
[1]);
306 uart_writeuint32(profile
.mode_registers
[2]);
308 uart_writeuint32(profile
.mode_registers
[3]);
312 // Early read test for WB access sim
313 //uart_writeuint32(*ram);
317 for (size_t i
= 0; i
< 8; i
++) {
318 profile2
.rdly_p0
= i
;
319 gram_load_calibration(&ctx
, &profile2
);
320 gram_reset_burstdet(&ctx
);
322 for (size_t j
= 0; j
< 128; j
++) {
323 tmp
= readl((unsigned long)&(ram
[i
]));
325 if (gram_read_burstdet(&ctx
, 0)) {
334 for (size_t i
= 0; i
< 8; i
++) {
335 profile2
.rdly_p1
= i
;
336 gram_load_calibration(&ctx
, &profile2
);
337 gram_reset_burstdet(&ctx
);
338 for (size_t j
= 0; j
< 128; j
++) {
339 tmp
= readl((unsigned long)&(ram
[i
]));
341 if (gram_read_burstdet(&ctx
, 1)) {
349 puts("Auto calibrating... ");
350 res
= gram_generate_calibration(&ctx
, &profile2
);
351 if (res
!= GRAM_ERR_NONE
) {
353 gram_load_calibration(&ctx
, &profile
);
355 gram_load_calibration(&ctx
, &profile2
);
359 puts("Auto calibration profile:");
361 uart_writeuint32(profile2
.rdly_p0
);
363 uart_writeuint32(profile2
.rdly_p1
);
367 puts("Reloading built-in calibration profile...");
368 gram_load_calibration(&ctx
, &profile
);
370 puts("DRAM test... \n");
371 for (size_t i
= 0; i
< kNumIterations
; i
++) {
372 writel(0xDEAF0000 | i
*4, (unsigned long)&(ram
[i
]));
376 for (int dly
= 0; dly
< 8; dly
++) {
378 profile2
.rdly_p0
= dly
;
379 profile2
.rdly_p1
= dly
;
381 uart_writeuint32(profile2
.rdly_p0
);
383 uart_writeuint32(profile2
.rdly_p1
);
384 gram_load_calibration(&ctx
, &profile2
);
385 for (size_t i
= 0; i
< kNumIterations
; i
++) {
386 if (readl((unsigned long)&(ram
[i
])) != (0xDEAF0000 | i
*4)) {
388 uart_writeuint32((unsigned long)(&ram
[i
]));
390 uart_writeuint32(readl((unsigned long)&(ram
[i
])));
395 puts("Test canceled (more than 10 errors)\n");
403 for (size_t i
= 0; i
< kNumIterations
; i
++) {
404 if (readl((unsigned long)&(ram
[i
])) != (0xDEAF0000 | i
*4)) {
406 uart_writeuint32((unsigned long)(&ram
[i
]));
408 uart_writeuint32(readl((unsigned long)&(ram
[i
])));
413 puts("Test canceled (more than 10 errors)\n");
418 if (failcnt
== 0) { // fiinally...
425 // memcpy from SPI Flash to SDRAM then boot
426 if ((ftr
& SYS_REG_INFO_HAS_SPI_FLASH
) &&
427 (ftr
& SYS_REG_INFO_HAS_DRAM
) &&
430 // identify ELF, copy if present, and get the start address
431 unsigned long faddr
= copy_flash(spi_offs
);
433 // jump to absolute address