coldboot/coldboot.c

   1 #include <stdint.h>
   2 #include <stdbool.h>
   3
   4 #include "console.h"
   5 #include "microwatt_soc.h"
   6 #include "io.h"
   7
   8 #include <stdlib.h>
   9 #include <stdint.h>
  10 #include <gram.h>
  11
  12 static inline uint32_t read32(const void *addr)
  13 {
  14         return *(volatile uint32_t *)addr;
  15 }
  16
  17 static inline void write32(void *addr, uint32_t value)
  18 {
  19         *(volatile uint32_t *)addr = value;
  20 }
  21
  22 struct uart_regs {
  23         uint32_t divisor;
  24         uint32_t rx_data;
  25         uint32_t rx_rdy;
  26         uint32_t rx_err;
  27         uint32_t tx_data;
  28         uint32_t tx_rdy;
  29         uint32_t zero0; // reserved
  30         uint32_t zero1; // reserved
  31         uint32_t ev_status;
  32         uint32_t ev_pending;
  33         uint32_t ev_enable;
  34 };
  35
  36 void memcpy(void *dest, void *src, size_t n) {
  37    int i;
  38    //cast src and dest to char*
  39    char *src_char = (char *)src;
  40    char *dest_char = (char *)dest;
  41    for (i=0; i<n; i++)
  42           dest_char[i] = src_char[i]; //copy contents byte by byte
  43 }
  44
  45 void uart_writeuint32(uint32_t val) {
  46         const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7',
  47                          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
  48         uint8_t *val_arr = &val;
  49         size_t i;
  50
  51         for (i = 0; i < 4; i++) {
  52                 putchar(lut[(val_arr[3-i] >> 4) & 0xF]);
  53                 putchar(lut[val_arr[3-i] & 0xF]);
  54         }
  55 }
  56
  57 void isr(void) {
  58
  59 }
  60
  61 int main(void) {
  62         const int kNumIterations = 14;
  63         int res, failcnt = 0;
  64         uint32_t tmp;
  65         volatile uint32_t *ram = DRAM_BASE;
  66         console_init();
  67         //puts("Firmware launched...\n");
  68
  69         puts("DRAM init... ");
  70         struct gramCtx ctx;
  71         struct gramProfile profile = {
  72                 .mode_registers = {
  73                         0x320, 0x6, 0x200, 0x0
  74                 },
  75                 .rdly_p0 = 5,
  76                 .rdly_p1 = 5,
  77         };
  78         struct gramProfile profile2;
  79         gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000,
  80                               (void*)DRAM_CTRL_BASE, //0x00009000,
  81                               (void*)DRAM_INIT_BASE); //0x00008000);
  82         puts("done\n");
  83
  84 #if 0
  85     // quick write/read
  86     writel(0xDEAF0000, (unsigned long)&(ram[0]));
  87     tmp = readl((unsigned long)&(ram[0]));
  88         puts("read ");
  89         uart_writeuint32(tmp);
  90
  91     return 0;
  92 #endif
  93
  94 #if 1
  95         puts("Rdly\np0: ");
  96         for (size_t i = 0; i < 8; i++) {
  97                 profile2.rdly_p0 = i;
  98                 gram_load_calibration(&ctx, &profile2);
  99                 gram_reset_burstdet(&ctx);
 100
 101                 for (size_t j = 0; j < 128; j++) {
 102                         tmp = readl((unsigned long)&(ram[i]));
 103                 }
 104                 if (gram_read_burstdet(&ctx, 0)) {
 105                         puts("1");
 106                 } else {
 107                         puts("0");
 108                 }
 109         }
 110         puts("\n");
 111
 112         puts("Rdly\np1: ");
 113         for (size_t i = 0; i < 8; i++) {
 114                 profile2.rdly_p1 = i;
 115                 gram_load_calibration(&ctx, &profile2);
 116                 gram_reset_burstdet(&ctx);
 117                 for (size_t j = 0; j < 128; j++) {
 118                         tmp = readl((unsigned long)&(ram[i]));
 119                 }
 120                 if (gram_read_burstdet(&ctx, 1)) {
 121                         puts("1");
 122                 } else {
 123                         puts("0");
 124                 }
 125         }
 126         puts("\n");
 127
 128         puts("Auto calibrating... ");
 129         res = gram_generate_calibration(&ctx, &profile2);
 130         if (res != GRAM_ERR_NONE) {
 131                 puts("failed\n");
 132                 gram_load_calibration(&ctx, &profile);
 133         } else {
 134                 gram_load_calibration(&ctx, &profile2);
 135         }
 136         puts("done\n");
 137
 138 #endif
 139
 140         puts("Auto calibration profile:");
 141         puts("p0 rdly:");
 142         uart_writeuint32(profile2.rdly_p0);
 143         puts(" p1 rdly:");
 144         uart_writeuint32(profile2.rdly_p1);
 145         puts("\n");
 146
 147         puts("DRAM test... \n");
 148         for (size_t i = 0; i < kNumIterations; i++) {
 149                 writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
 150         }
 151
 152         for (int dly = 0; dly < 8; dly++) {
 153         failcnt = 0;
 154         profile2.rdly_p0 = dly;
 155         profile2.rdly_p1 = dly;
 156         puts("p0 rdly:");
 157         uart_writeuint32(profile2.rdly_p0);
 158         puts(" p1 rdly:");
 159         uart_writeuint32(profile2.rdly_p1);
 160                 gram_load_calibration(&ctx, &profile2);
 161         for (size_t i = 0; i < kNumIterations; i++) {
 162             if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
 163                 puts("fail : *(0x");
 164                 uart_writeuint32(&ram[i]);
 165                 puts(") = ");
 166                 uart_writeuint32(ram[i]);
 167                 puts("\n");
 168                 failcnt++;
 169
 170                 if (failcnt > 10) {
 171                     puts("Test canceled (more than 10 errors)\n");
 172                     break;
 173                 }
 174             }
 175         }
 176     }
 177         puts("done\n");
 178
 179         return 0;
 180 }
 181