2 def __init__(self
, crg0
, norflash0
, uart0
, ddrphy0
, minimac0
, fb0
):
4 def add(signal
, pin
, vec
=-1, iostandard
="LVCMOS33", extra
=""):
5 self
.constraints
.append((signal
, vec
, pin
, iostandard
, extra
))
6 def add_vec(signal
, pins
, iostandard
="LVCMOS33", extra
=""):
7 assert(signal
.bv
.width
== len(pins
))
10 add(signal
, p
, i
, iostandard
, extra
)
13 add(crg0
.clkin
, "AB11", extra
="TNM_NET = \"GRPclk50\"")
14 add(crg0
.ac97_rst_n
, "D6")
15 add(crg0
.videoin_rst_n
, "W17")
16 add(crg0
.flash_rst_n
, "P22", extra
="SLEW = FAST | DRIVE = 8")
17 add(crg0
.trigger_reset
, "AA4")
18 add(crg0
.eth_clk_pad
, "M20")
19 add(crg0
.vga_clk_pad
, "A11")
21 add_vec(norflash0
.adr
, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
22 "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
23 "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
24 extra
="SLEW = FAST | DRIVE = 8")
25 add_vec(norflash0
.d
, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
26 "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
27 extra
="SLEW = FAST | DRIVE = 8 | PULLDOWN")
28 add(norflash0
.oe_n
, "M22", extra
="SLEW = FAST | DRIVE = 8")
29 add(norflash0
.we_n
, "N20", extra
="SLEW = FAST | DRIVE = 8")
30 add(norflash0
.ce_n
, "M21", extra
="SLEW = FAST | DRIVE = 8")
32 add(uart0
.tx
, "L17", extra
="SLEW = SLOW")
33 add(uart0
.rx
, "K18", extra
="PULLUP")
35 ddrsettings
= "IOSTANDARD = SSTL2_I"
36 add(ddrphy0
.sd_clk_out_p
, "M3", extra
=ddrsettings
)
37 add(ddrphy0
.sd_clk_out_n
, "L4", extra
=ddrsettings
)
38 add_vec(ddrphy0
.sd_a
, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
39 "G6", "C1", "C3", "D1", "D2"], extra
=ddrsettings
)
40 add_vec(ddrphy0
.sd_ba
, ["A2", "E6"], extra
=ddrsettings
)
41 add(ddrphy0
.sd_cs_n
, "F7", extra
=ddrsettings
)
42 add(ddrphy0
.sd_cke
, "G7", extra
=ddrsettings
)
43 add(ddrphy0
.sd_ras_n
, "E5", extra
=ddrsettings
)
44 add(ddrphy0
.sd_cas_n
, "C4", extra
=ddrsettings
)
45 add(ddrphy0
.sd_we_n
, "D3", extra
=ddrsettings
)
46 add_vec(ddrphy0
.sd_dq
, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
47 "U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
48 "M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
50 add_vec(ddrphy0
.sd_dm
, ["E1", "E3", "F3", "G4"], extra
=ddrsettings
)
51 add_vec(ddrphy0
.sd_dqs
, ["F1", "F2", "H5", "H6"], extra
=ddrsettings
)
53 add(minimac0
.phy_rst_n
, "R22")
54 add(minimac0
.phy_dv
, "V21")
55 add(minimac0
.phy_rx_clk
, "H22")
56 add(minimac0
.phy_rx_er
, "V22")
57 add_vec(minimac0
.phy_rx_data
, ["U22", "U20", "T22", "T21"])
58 add(minimac0
.phy_tx_en
, "N19")
59 add(minimac0
.phy_tx_clk
, "H21")
60 add(minimac0
.phy_tx_er
, "M19")
61 add_vec(minimac0
.phy_tx_data
, ["M16", "L15", "P19", "P20"])
62 add(minimac0
.phy_col
, "W20")
63 add(minimac0
.phy_crs
, "W22")
65 add_vec(fb0
.vga_r
, ["C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9"])
66 add_vec(fb0
.vga_g
, ["C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10"])
67 add_vec(fb0
.vga_b
, ["D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14"])
68 add(fb0
.vga_hsync_n
, "A14")
69 add(fb0
.vga_vsync_n
, "C15")
70 add(fb0
.vga_psave_n
, "B14")
72 self
._phy
_rx
_clk
= minimac0
.phy_rx_clk
73 self
._phy
_tx
_clk
= minimac0
.phy_tx_clk
76 return set([c
[0] for c
in self
.constraints
])
78 def get_ucf(self
, ns
):
80 for c
in self
.constraints
:
81 r
+= "NET \"" + ns
.get_name(c
[0])
83 r
+= "(" + str(c
[1]) + ")"
84 r
+= "\" LOC = " + c
[2]
85 r
+= " | IOSTANDARD = " + c
[3]
91 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
92 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
93 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
95 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
97 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
98 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
99 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
100 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
101 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
102 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
104 NET "asfifo*/counter_read/gray_count*" TIG;
105 NET "asfifo*/counter_write/gray_count*" TIG;
106 NET "asfifo*/preset_empty*" TIG;
108 """.format(phy_rx_clk
=ns
.get_name(self
._phy
_rx
_clk
), phy_tx_clk
=ns
.get_name(self
._phy
_tx
_clk
))