Initial import
[litex.git] / constraints.py
1 def Get(ns, norflash0, uart0):
2 constraints = []
3 def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
4 constraints.append((ns.GetName(signal), vec, pin, iostandard, extra))
5 def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
6 i = 0
7 for p in pins:
8 add(signal, p, i, iostandard, extra)
9 i += 1
10
11 add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
12 "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
13 "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
14 extra="SLEW = FAST | DRIVE = 8")
15 add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
16 "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
17 extra = "SLEW = FAST | DRIVE = 8 | PULLDOWN")
18 add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
19 add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
20 add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
21 add(norflash0.rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
22
23 add(uart0.tx, "L17", extra="SLEW = SLOW")
24 add(uart0.rx, "K18", extra="PULLUP")
25
26 r = ""
27 for c in constraints:
28 r += "NET \"" + c[0]
29 if c[1] >= 0:
30 r += "(" + str(c[1]) + ")"
31 r += "\" LOC = " + c[2]
32 r += " | IOSTANDARD = " + c[3]
33 if c[4]:
34 r += " | " + c[4]
35 r += ";\n"
36
37 r += """
38 NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
39 NET "sys_clk" TNM_NET = "GRPclk50";
40 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
41
42 NET "sys_rst" LOC = AA4 | IOSTANDARD = LVCMOS33;
43 """
44
45 return r