Generate all clocks for the DDR PHY
[litex.git] / constraints.py
1 def get(ns, crg0, norflash0, uart0):
2 constraints = []
3 def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
4 constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
5 def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
6 i = 0
7 for p in pins:
8 add(signal, p, i, iostandard, extra)
9 i += 1
10
11 add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
12 add(crg0.ac97_rst_n, "D6")
13 add(crg0.videoin_rst_n, "W17")
14 add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
15 add(crg0.rd_clk_lb, "K5")
16 add(crg0.trigger_reset, "AA4")
17
18 add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
19 "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
20 "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
21 extra="SLEW = FAST | DRIVE = 8")
22 add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
23 "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
24 extra = "SLEW = FAST | DRIVE = 8 | PULLDOWN")
25 add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
26 add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
27 add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
28
29 add(uart0.tx, "L17", extra="SLEW = SLOW")
30 add(uart0.rx, "K18", extra="PULLUP")
31
32 r = ""
33 for c in constraints:
34 r += "NET \"" + c[0]
35 if c[1] >= 0:
36 r += "(" + str(c[1]) + ")"
37 r += "\" LOC = " + c[2]
38 r += " | IOSTANDARD = " + c[3]
39 if c[4]:
40 r += " | " + c[4]
41 r += ";\n"
42
43 r += """
44 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
45 """
46
47 return r