12 temporary_binary
= None
17 def __init__(self
, server_cmd
, sim_cmd
, isolate
):
18 self
.server_cmd
= server_cmd
19 self
.sim_cmd
= sim_cmd
20 self
.isolate
= isolate
23 """Start the target, eg. a simulator."""
27 """Start the debug server that gdb connects to, eg. OpenOCD."""
28 if self
.openocd_config
:
29 return testlib
.Openocd(server_cmd
=self
.server_cmd
, config
=self
.openocd_config
)
31 raise NotImplementedError
33 def compile(self
, *sources
):
34 binary_name
= "%s_%s-%d" % (
36 os
.path
.basename(os
.path
.splitext(sources
[0])[0]),
39 self
.temporary_binary
= tempfile
.NamedTemporaryFile(
40 prefix
=binary_name
+ "_")
41 binary_name
= self
.temporary_binary
.name
42 Target
.temporary_files
.append(self
.temporary_binary
)
43 march
= "rv%dima" % self
.xlen
46 if self
.extensionSupported("c"):
48 testlib
.compile(sources
+
49 ("programs/entry.S", "programs/init.c",
52 "-T", "targets/%s/link.lds" % (self
.directory
or self
.name
),
55 "-DXLEN=%d" % self
.xlen
,
60 def extensionSupported(self
, letter
):
61 # target.misa is set by testlib.ExamineTarget
62 return self
.misa
& (1 << (ord(letter
.upper()) - ord('A')))
64 class SpikeTarget(Target
):
65 # pylint: disable=abstract-method
69 instruction_hardware_breakpoint_count
= 4
71 openocd_config
= "targets/%s/openocd.cfg" % directory
73 class Spike64Target(SpikeTarget
):
79 return testlib
.Spike(self
.sim_cmd
)
81 class Spike32Target(SpikeTarget
):
86 return testlib
.Spike(self
.sim_cmd
, xlen
=32)
88 class FreedomE300Target(Target
):
93 instruction_hardware_breakpoint_count
= 2
94 openocd_config
= "targets/%s/openocd.cfg" % name
96 class HiFive1Target(FreedomE300Target
):
98 openocd_config
= "targets/%s/openocd.cfg" % name
100 class FreedomE300SimTarget(Target
):
101 name
= "freedom-e300-sim"
105 ram_size
= 256 * 1024 * 1024
106 instruction_hardware_breakpoint_count
= 2
107 openocd_config
= "targets/%s/openocd.cfg" % name
110 return testlib
.VcsSim(sim_cmd
=self
.sim_cmd
, debug
=False)
112 class FreedomU500Target(Target
):
113 name
= "freedom-u500"
117 instruction_hardware_breakpoint_count
= 2
118 openocd_config
= "targets/%s/openocd.cfg" % name
120 class FreedomU500SimTarget(Target
):
121 name
= "freedom-u500-sim"
125 ram_size
= 256 * 1024 * 1024
126 instruction_hardware_breakpoint_count
= 2
127 openocd_config
= "targets/%s/openocd.cfg" % name
130 return testlib
.VcsSim(sim_cmd
=self
.sim_cmd
, debug
=False)
137 FreedomE300SimTarget
,
138 FreedomU500SimTarget
,
141 def add_target_options(parser
):
142 group
= parser
.add_mutually_exclusive_group(required
=True)
144 group
.add_argument("--%s" % t
.name
, action
="store_const", const
=t
,
146 parser
.add_argument("--sim_cmd",
147 help="The command to use to start the actual target (e.g. "
149 parser
.add_argument("--server_cmd",
150 help="The command to use to start the debug server (e.g. OpenOCD)")
152 xlen_group
= parser
.add_mutually_exclusive_group()
153 xlen_group
.add_argument("--32", action
="store_const", const
=32, dest
="xlen",
154 help="Force the target to be 32-bit.")
155 xlen_group
.add_argument("--64", action
="store_const", const
=64, dest
="xlen",
156 help="Force the target to be 64-bit.")
158 parser
.add_argument("--isolate", action
="store_true",
159 help="Try to run in such a way that multiple instances can run at "
160 "the same time. This may make it harder to debug a failure if it "