1 from migen
.fhdl
.std
import *
2 from migen
.fhdl
import verilog
3 from migen
.genlib
.record
import *
10 ("color", 32, DIR_M_TO_S
),
11 ("stb", 1, DIR_M_TO_S
),
12 ("ack", 1, DIR_S_TO_M
)
19 self
.comb
+= master
.connect(slave
)
21 print(verilog
.convert(Test()))
23 print(layout_partial(L
, "position/x", "color"))