examples/basic/record.py

   1 from migen.fhdl.std import *
   2 from migen.fhdl import verilog
   3 from migen.genlib.record import *
   4
   5 L = [
   6         ("position", [
   7                         ("x", 10, DIR_M_TO_S),
   8                         ("y", 10, DIR_M_TO_S),
   9         ]),
  10         ("color", 32, DIR_M_TO_S),
  11         ("stb", 1, DIR_M_TO_S),
  12         ("ack", 1, DIR_S_TO_M)
  13 ]
  14
  15 class Test(Module):
  16         def __init__(self):
  17                 master = Record(L)
  18                 slave = Record(L)
  19                 self.comb += master.connect(slave)
  20
  21 print(verilog.convert(Test()))
  22 print(layout_len(L))
  23 print(layout_partial(L, "position/x", "color"))