examples/basic/reslice.py

   1 from migen import *
   2 from migen.fhdl import verilog
   3
   4
   5 class Example(Module):
   6     def __init__(self):
   7         a = Signal(3)
   8         b = Signal(4)
   9         c = Signal(5)
  10         d = Signal(7)
  11         s1 = c[:3][:2]
  12         s2 = Cat(a, b)[:6]
  13         s3 = Cat(s1, s2)[-5:]
  14         self.comb += s3.eq(0)
  15         self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
  16
  17
  18 if __name__ == "__main__":
  19     print(verilog.convert(Example()))