sim: VCD generation
[litex.git] / examples / basic_sim.py
1 from migen.fhdl.structure import *
2 from migen.sim.generic import Simulator, TopLevel
3 from migen.sim.icarus import Runner
4
5 class Counter:
6 def __init__(self):
7 self.ce = Signal()
8 self.count = Signal(BV(4))
9
10 def do_simulation(self, s, cycle):
11 if cycle % 2:
12 s.wr(self.ce, 0)
13 else:
14 s.wr(self.ce, 1)
15 print("Cycle: " + str(cycle) + " Count: " + str(s.rd(self.count)))
16
17 def get_fragment(self):
18 sync = [If(self.ce, self.count.eq(self.count + 1))]
19 sim = [self.do_simulation]
20 return Fragment(sync=sync, sim=sim)
21
22 def main():
23 dut = Counter()
24 sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
25 sim.run(10)
26
27 main()