2 def __init__(self
, in_rst_n
, cd_in
, spi2csr0
, led0
, sw0
):
4 def add(signal
, pin
, vec
=-1, iostandard
="3.3-V LVTTL", extra
="", sch
=""):
5 self
.constraints
.append((signal
, vec
, pin
, iostandard
, extra
,sch
))
6 def add_vec(signal
, pins
, iostandard
="3.3-V LVTTL", extra
="", sch
=""):
7 assert(signal
.nbits
== len(pins
)), "%s size : %d / qsf size : %d" %(signal
,signal
.bv
.width
,len(pins
))
10 add(signal
, p
, i
, iostandard
, extra
)
13 add(cd_in
.clk
, "L1") # CLOCK_50
16 add(in_rst_n
, "R22") # KEY[0]
19 add(spi2csr0
.spi_clk
, "F13") #GPIO_1[9]
20 add(spi2csr0
.spi_cs_n
, "G15") #GPIO_1[3]
21 add(spi2csr0
.spi_mosi
, "E15") #GPIO_1[5]
22 add(spi2csr0
.spi_miso
, "G16") #GPIO_1[7]
25 add_vec(led0
, ["U22", "U21", "V22", "V21",
26 "W22" , "W21" , "Y22" , "Y21"])
28 add_vec(sw0
, ["L22", "L21", "M22", "V12",
29 "W12" , "U12" , "U11" , "M2"])
32 return set([c
[0] for c
in self
.constraints
])
34 def get_qsf(self
, ns
):
36 for c
in self
.constraints
:
37 r
+= "set_location_assignment PIN_"+str(c
[2])
38 r
+= " -to " + ns
.get_name(c
[0])
40 r
+= "[" + str(c
[1]) + "]"
43 r
+= "set_instance_assignment -name IO_STANDARD "
44 r
+= "\"" + c
[3] + "\""
45 r
+= " -to " + ns
.get_name(c
[0])
47 r
+= "[" + str(c
[1]) + "]"
51 set_global_assignment -name FAMILY "Cyclone II"
52 set_global_assignment -name DEVICE EP2C20F484C7
53 set_global_assignment -name TOP_LEVEL_ENTITY "de1"
54 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
55 set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
56 set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
57 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
58 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
59 set_global_assignment -name DUTY_CYCLE 50 -section_id in_clk
60 set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz" -section_id in_clk