examples/pytholite/basic: demonstrate conversion to Verilog
[litex.git] / examples / pytholite / basic.py
1 from migen.flow.network import *
2 from migen.actorlib.sim import *
3 from migen.pytholite.compiler import make_pytholite
4 from migen.sim.generic import Simulator
5 from migen.sim.icarus import Runner
6 from migen.fhdl import verilog
7
8 layout = [("r", BV(32))]
9
10 def number_gen():
11 for i in range(10):
12 yield Token("result", {"r": i})
13
14 class Dumper(SimActor):
15 def __init__(self):
16 def dumper_gen():
17 while True:
18 t = Token("result")
19 yield t
20 print(t.value["r"])
21 super().__init__(dumper_gen(),
22 ("result", Sink, layout))
23
24 def run_sim(ng):
25 g = DataFlowGraph()
26 d = Dumper()
27 g.add_connection(ActorNode(ng), ActorNode(d))
28
29 c = CompositeActor(g)
30 fragment = c.get_fragment()
31 sim = Simulator(fragment, Runner())
32 sim.run(30)
33 del sim
34
35 def main():
36 print("Simulating native Python:")
37 ng_native = SimActor(number_gen(), ("result", Source, layout))
38 run_sim(ng_native)
39
40 print("Simulating Pytholite:")
41 ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
42 run_sim(ng_pytholite)
43
44 print("Converting Pytholite to Verilog:")
45 print(verilog.convert(ng_pytholite.get_fragment()))
46
47 main()