1 from random
import Random
3 from migen
.fhdl
.structure
import *
4 from migen
.fhdl
import autofragment
5 from migen
.bus
.transactions
import *
6 from migen
.bus
import wishbone
7 from migen
.sim
.generic
import Simulator
8 from migen
.sim
.icarus
import Runner
15 print("Wrote in " + str(t
.latency
) + " cycle(s)")
16 for delay
in range(prng
.randrange(0, 3)):
21 print("Read " + str(t
.data
) + " in " + str(t
.latency
) + " cycle(s)")
22 for delay
in range(prng
.randrange(0, 3)):
27 self
.bus
= wishbone
.Interface()
28 self
.ack_en
= Signal()
29 self
.prng
= Random(763627)
31 def do_simulation(self
, s
):
32 # Only authorize acks on certain cycles to simulate variable latency
33 s
.wr(self
.ack_en
, self
.prng
.randrange(0, 2))
35 def get_fragment(self
):
37 self
.bus
.ack
.eq(self
.bus
.cyc
& self
.bus
.stb
& self
.ack_en
),
38 self
.bus
.dat_r
.eq(self
.bus
.adr
+ 4)
40 return Fragment(comb
, sim
=[self
.do_simulation
])
43 master
= wishbone
.Initiator(my_generator())
44 slave
= MyPeripheral()
45 tap
= wishbone
.Tap(slave
.bus
)
46 intercon
= wishbone
.InterconnectPointToPoint(master
.bus
, slave
.bus
)
47 def end_simulation(s
):
48 s
.interrupt
= master
.done
49 fragment
= autofragment
.from_local() + Fragment(sim
=[end_simulation
])
50 sim
= Simulator(fragment
, Runner())