bus: generic transaction model
[litex.git] / examples / wb_initiator.py
1 from random import Random
2
3 from migen.fhdl.structure import *
4 from migen.fhdl import autofragment
5 from migen.bus.transactions import *
6 from migen.bus import wishbone
7 from migen.sim.generic import Simulator
8 from migen.sim.icarus import Runner
9
10 def my_generator():
11 prng = Random(92837)
12 for x in range(10):
13 t = TWrite(x, 2*x)
14 yield t
15 print("Wrote in " + str(t.latency) + " cycle(s)")
16 for delay in range(prng.randrange(0, 3)):
17 yield None
18 for x in range(10):
19 t = TRead(x)
20 yield t
21 print("Read " + str(t.data) + " in " + str(t.latency) + " cycle(s)")
22 for delay in range(prng.randrange(0, 3)):
23 yield None
24
25 class MyPeripheral:
26 def __init__(self):
27 self.bus = wishbone.Interface()
28 self.ack_en = Signal()
29 self.prng = Random(763627)
30
31 def do_simulation(self, s):
32 # Only authorize acks on certain cycles to simulate variable latency
33 s.wr(self.ack_en, self.prng.randrange(0, 2))
34
35 def get_fragment(self):
36 comb = [
37 self.bus.ack.eq(self.bus.cyc & self.bus.stb & self.ack_en),
38 self.bus.dat_r.eq(self.bus.adr + 4)
39 ]
40 return Fragment(comb, sim=[self.do_simulation])
41
42 def main():
43 master = wishbone.Initiator(my_generator())
44 slave = MyPeripheral()
45 tap = wishbone.Tap(slave.bus)
46 intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
47 def end_simulation(s):
48 s.interrupt = master.done
49 fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
50 sim = Simulator(fragment, Runner())
51 sim.run()
52
53 main()