1 // Copyright 2017 Gnarly Grey LLC
3 // Permission is hereby granted, free of charge, to any person obtaining a
4 // copy of this software and associated documentation files (the
5 // "Software"), to deal in the Software without restriction, including
6 // without limitation the rights to use, copy, modify, merge, publish,
7 // distribute, sublicense, and/or sell copies of the Software, and to
8 // permit persons to whom the Software is furnished to do so, subject to
9 // the following conditions:
11 // The above copyright notice and this permission notice shall be included
12 // in all copies or substantial portions of the Software.
14 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 // OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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20 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 input [3:0] i_mem_wstrb,
32 input [31:0] i_mem_addr,
33 input [31:0] i_mem_wdata,
34 output [31:0] o_mem_rdata,
52 parameter WR_LATENCY = 2;
58 parameter WRITE_LATENCY = 6*2+10 - 1;
71 wire [7:0] ca_words[5:0];
72 wire [7:0] wdata_words[3:0];
73 wire [3:0] wstrb_words;
76 always @(posedge i_clk or negedge i_rstn) begin
86 IDLE : begin// wait for mem transaction
88 if(i_mem_valid && !mem_ready) begin
89 ca[47] <= ~(|i_mem_wstrb);
90 ca[46] <= i_cfg_access;
91 ca[45] <= (|i_mem_wstrb) & i_cfg_access;
92 ca[44:16] <= i_mem_addr[31:3];
94 ca[2:0] <= i_mem_addr[2:0];
103 counter <= counter - 1;
104 end else if(ca[47]) begin // read
108 if (ca[46]) begin // write to register
111 end else begin // write to memory
112 counter <= WRITE_LATENCY;
119 counter <= counter - 1;
127 counter <= counter - 1;
135 3: mem_rdata[15:8] <= i_dq;
136 2: mem_rdata[7:0] <= i_dq;
137 1: mem_rdata[31:24] <= i_dq;
138 0: mem_rdata[23:16] <= i_dq;
141 counter <= counter - 1;
155 assign rwds_valid = (rwds_d | i_rwds);
156 assign ca_words[5] = ca[47:40];
157 assign ca_words[4] = ca[39:32];
158 assign ca_words[3] = ca[31:24];
159 assign ca_words[2] = ca[23:16];
160 assign ca_words[1] = ca[15:8];
161 assign ca_words[0] = ca[7:0];
162 assign wdata_words[3] = wdata[15:8];
163 assign wdata_words[2] = wdata[7:0];
164 assign wdata_words[1] = ca[46]?wdata[15:8]:wdata[31:24];
165 assign wdata_words[0] = ca[46]?wdata[7:0]:wdata[23:16];
166 assign wstrb_words = {wstrb[1], wstrb[0], wstrb[3], wstrb[2]};
169 always @(negedge i_clk or negedge i_rstn) begin
173 bus_clk <= o_csn0 ? 0 : ~bus_clk;
176 assign o_csn0 = (state == IDLE || state == DONE);
177 assign o_csn1 = 1'b1;
178 assign o_clk = bus_clk;
179 assign o_clkn = ~o_clk;
180 assign o_resetn = i_rstn;
181 assign o_dq = (state == CAs)? ca_words[counter]:
182 (state == WRITE)? wdata_words[counter]:8'h0;
183 assign o_rwds = (state == WRITE)? ~wstrb_words[counter]:1'b0;
184 assign o_dq_de = (state == WRITE || state == CAs);
185 assign o_rwds_de = (state == WRITE) && (~ca[46]);
186 assign o_mem_ready = mem_ready;
187 assign o_mem_rdata = mem_rdata;