include/microwatt_soc.h

   1 /* This code is directly from Microwatt and is Copyright and Licensed
   2    under the same terms as Microwatt source code.
   3 https://github.com/antonblanchard/microwatt/blob/master/include/microwatt_soc.h
   4 */
   5
   6 #ifndef __MICROWATT_SOC_H
   7 #define __MICROWATT_SOC_H
   8
   9 /*
  10  * Microwatt SoC memory map
  11  */
  12
  13 #define MEMORY_BASE     0x00000000  /* "Main" memory alias, either BRAM or DRAM */
  14 #define DRAM_BASE       0x40000000  /* DRAM if present */
  15 #define BRAM_BASE       0x80000000  /* Internal BRAM */
  16
  17 #define SYSCON_BASE     0xc0000000  /* System control regs */
  18 #define UART_BASE       0xc0002000  /* UART */
  19 #define XICS_ICP_BASE   0xc0004000  /* Interrupt controller */
  20 #define XICS_ICS_BASE   0xc0005000  /* Interrupt controller */
  21 #define SPI_FCTRL_BASE  0xc0006000  /* SPI flash controller registers */
  22 #define DRAM_CTRL_BASE  0xc8000000  /* LiteDRAM control registers */
  23 #define LETH_CSR_BASE   0xc8020000  /* LiteEth CSR registers */
  24 #define LETH_SRAM_BASE  0xc8030000  /* LiteEth MMIO space */
  25 #define SPI_FLASH_BASE  0xf0000000  /* SPI Flash memory map */
  26 #ifdef STANDALONE_MINI_BIOS
  27 #define DRAM_INIT_BASE  0x00000000  /* alternative, for verilator simulation */
  28 #else
  29 #define DRAM_INIT_BASE  0xff000000  /* Internal DRAM init firmware */
  30 #endif
  31
  32 /*
  33  * Interrupt numbers
  34  */
  35 #define IRQ_UART0       0
  36 #define IRQ_ETHERNET    1
  37
  38 /*
  39  * Register definitions for the syscon registers
  40  */
  41
  42 #define SYS_REG_SIGNATURE               0x00
  43 #define SYS_REG_INFO                    0x08
  44 #define   SYS_REG_INFO_HAS_UART                 (1ull << 0)
  45 #define   SYS_REG_INFO_HAS_DRAM                 (1ull << 1)
  46 #define   SYS_REG_INFO_HAS_BRAM                 (1ull << 2)
  47 #define   SYS_REG_INFO_HAS_SPI_FLASH            (1ull << 3)
  48 #define   SYS_REG_INFO_HAS_LITEETH              (1ull << 4)
  49 #define   SYS_REG_INFO_HAS_LARGE_SYSCON         (1ull << 5)
  50 #define   SYS_REG_INFO_HAS_UART1                (1ull << 6)
  51 #define   SYS_REG_INFO_HAS_ARTB                 (1ull << 7)
  52 #define SYS_REG_BRAMINFO                0x10
  53 #define   SYS_REG_BRAMINFO_SIZE_MASK            0xfffffffffffffull
  54 #define SYS_REG_DRAMINFO                0x18
  55 #define   SYS_REG_DRAMINFO_SIZE_MASK            0xfffffffffffffull
  56 #define SYS_REG_CLKINFO                 0x20
  57 #define   SYS_REG_CLKINFO_FREQ_MASK             0xffffffffffull
  58 #define SYS_REG_CTRL                    0x28
  59 #define   SYS_REG_CTRL_DRAM_AT_0                (1ull << 0)
  60 #define   SYS_REG_CTRL_CORE_RESET               (1ull << 1)
  61 #define   SYS_REG_CTRL_SOC_RESET                (1ull << 2)
  62 #define SYS_REG_DRAMINITINFO            0x30
  63 #define SYS_REG_SPI_INFO                0x38
  64 #define   SYS_REG_SPI_INFO_FLASH_OFF_MASK       0xffffffff
  65 #define SYS_REG_UART0_INFO              0x40
  66 #define SYS_REG_UART1_INFO              0x48
  67 #define   SYS_REG_UART_IS_16550                 (1ull << 32)
  68 #define SYS_REG_BRAM_BOOTADDR           0x50
  69
  70
  71 /*
  72  * Register definitions for the potato UART
  73  */
  74 #define POTATO_CONSOLE_TX               0x00
  75 #define POTATO_CONSOLE_RX               0x08
  76 #define POTATO_CONSOLE_STATUS           0x10
  77 #define   POTATO_CONSOLE_STATUS_RX_EMPTY                0x01
  78 #define   POTATO_CONSOLE_STATUS_TX_EMPTY                0x02
  79 #define   POTATO_CONSOLE_STATUS_RX_FULL                 0x04
  80 #define   POTATO_CONSOLE_STATUS_TX_FULL                 0x08
  81 #define POTATO_CONSOLE_CLOCK_DIV        0x18
  82 #define POTATO_CONSOLE_IRQ_EN           0x20
  83 #define   POTATO_CONSOLE_IRQ_RX                         0x01
  84 #define   POTATO_CONSOLE_IRQ_TX                         0x02
  85
  86 /*
  87  * Register definitionss for our standard (16550 style) UART
  88  */
  89 #define UART_REG_RX       0x00
  90 #define UART_REG_TX       0x00
  91 #define UART_REG_DLL      0x00
  92 #define UART_REG_IER      0x04
  93 #define   UART_REG_IER_RDI      0x01
  94 #define   UART_REG_IER_THRI     0x02
  95 #define   UART_REG_IER_RLSI     0x04
  96 #define   UART_REG_IER_MSI      0x08
  97 #define UART_REG_DLM      0x04
  98 #define UART_REG_IIR      0x08
  99 #define UART_REG_FCR      0x08
 100 #define   UART_REG_FCR_EN_FIFO  0x01
 101 #define   UART_REG_FCR_CLR_RCVR 0x02
 102 #define   UART_REG_FCR_CLR_XMIT 0x04
 103 #define   UART_REG_FCR_TRIG1    0x00
 104 #define   UART_REG_FCR_TRIG4    0x40
 105 #define   UART_REG_FCR_TRIG8    0x80
 106 #define   UART_REG_FCR_TRIG14   0xc0
 107 #define UART_REG_LCR      0x0c
 108 #define   UART_REG_LCR_5BIT     0x00
 109 #define   UART_REG_LCR_6BIT     0x01
 110 #define   UART_REG_LCR_7BIT     0x02
 111 #define   UART_REG_LCR_8BIT     0x03
 112 #define   UART_REG_LCR_STOP     0x04
 113 #define   UART_REG_LCR_PAR      0x08
 114 #define   UART_REG_LCR_EVEN_PAR 0x10
 115 #define   UART_REG_LCR_STIC_PAR 0x20
 116 #define   UART_REG_LCR_BREAK    0x40
 117 #define   UART_REG_LCR_DLAB     0x80
 118 #define UART_REG_MCR      0x10
 119 #define   UART_REG_MCR_DTR      0x01
 120 #define   UART_REG_MCR_RTS      0x02
 121 #define   UART_REG_MCR_OUT1     0x04
 122 #define   UART_REG_MCR_OUT2     0x08
 123 #define   UART_REG_MCR_LOOP     0x10
 124 #define UART_REG_LSR      0x14
 125 #define   UART_REG_LSR_DR       0x01
 126 #define   UART_REG_LSR_OE       0x02
 127 #define   UART_REG_LSR_PE       0x04
 128 #define   UART_REG_LSR_FE       0x08
 129 #define   UART_REG_LSR_BI       0x10
 130 #define   UART_REG_LSR_THRE     0x20
 131 #define   UART_REG_LSR_TEMT     0x40
 132 #define   UART_REG_LSR_FIFOE    0x80
 133 #define UART_REG_MSR      0x18
 134 #define UART_REG_SCR      0x1c
 135
 136
 137 /*
 138  * Register definitions for the SPI controller
 139  */
 140 #define SPI_REG_DATA                    0x00 /* Byte access: single wire transfer */
 141 #define SPI_REG_DATA_DUAL               0x01 /* Byte access: dual wire transfer */
 142 #define SPI_REG_DATA_QUAD               0x02 /* Byte access: quad wire transfer */
 143 #define SPI_REG_CTRL                    0x04 /* Reset and manual mode control */
 144 #define   SPI_REG_CTRL_RESET                    0x01  /* reset all registers */
 145 #define   SPI_REG_CTRL_MANUAL_CS                0x02  /* assert CS, enable manual mode */
 146 #define   SPI_REG_CTRL_CKDIV_SHIFT              8     /* clock div */
 147 #define   SPI_REG_CTRL_CKDIV_MASK               (0xff << SPI_REG_CTRL_CKDIV_SHIFT)
 148 #define SPI_REG_AUTO_CFG                0x08 /* Automatic map configuration */
 149 #define   SPI_REG_AUTO_CFG_CMD_SHIFT            0     /* Command to use for reads */
 150 #define   SPI_REG_AUTO_CFG_CMD_MASK             (0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
 151 #define   SPI_REG_AUTO_CFG_DUMMIES_SHIFT        8     /* # dummy cycles */
 152 #define   SPI_REG_AUTO_CFG_DUMMIES_MASK         (0x7  << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
 153 #define   SPI_REG_AUTO_CFG_MODE_SHIFT           11    /* SPI wire mode */
 154 #define   SPI_REG_AUTO_CFG_MODE_MASK            (0x3  << SPI_REG_AUTO_CFG_MODE_SHIFT)
 155 #define     SPI_REG_AUT_CFG_MODE_SINGLE         (0 << 11)
 156 #define     SPI_REG_AUT_CFG_MODE_DUAL           (2 << 11)
 157 #define     SPI_REG_AUT_CFG_MODE_QUAD           (3 << 11)
 158 #define   SPI_REG_AUTO_CFG_ADDR4                (1u << 13) /* 3 or 4 addr bytes */
 159 #define   SPI_REG_AUTO_CFG_CKDIV_SHIFT          16    /* clock div */
 160 #define   SPI_REG_AUTO_CFG_CKDIV_MASK           (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
 161 #define   SPI_REG_AUTO_CFG_CSTOUT_SHIFT         24    /* CS timeout */
 162 #define   SPI_REG_AUTO_CFG_CSTOUT_MASK          (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
 163
 164
 165 #endif /* __MICROWATT_SOC_H */