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HEAD
correctly set SR_EA bit for all vector physical tests
[riscv-tests.git]
/
isa
/
rv64uv
/
vvadd_w.S
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#*****************************************************************************
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# vvadd_w.S
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#-----------------------------------------------------------------------------
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#
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# Test vvadd w.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64UV
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RVTEST_CODE_BEGIN
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vsetcfg 32,0
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li a3,9
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vsetvl a3,a3
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la a3,src1
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la a4,src2
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vlw vx2,a3
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vlw vx3,a4
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lui a0,%hi(vtcode)
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vf %lo(vtcode)(a0)
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la a5,dest
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vsw vx2,a5
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fence
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lw a1,0(a5)
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li a2,10
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li x28,2
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bne a1,a2,fail
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lw a1,4(a5)
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li x28,3
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bne a1,a2,fail
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lw a1,8(a5)
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li x28,4
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bne a1,a2,fail
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lw a1,12(a5)
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li x28,5
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bne a1,a2,fail
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j pass
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vtcode:
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addw x2,x2,x3
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stop
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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src1:
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.word 1
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.word 2
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.word 3
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.word 4
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.word 5
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.word 6
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.word 7
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.word 8
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.word 9
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src2:
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.word 9
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.word 8
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.word 7
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.word 6
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.word 5
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.word 4
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.word 3
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.word 2
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.word 1
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dest:
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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.word 0xdeadbeef
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RVTEST_DATA_END