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instanciate GTXE2_COMMON (seems recommended in AR43339)
[litex.git] / lib / sata / k7sataphy / gtx.py
1 from migen.fhdl.std import *
2 from migen.genlib.cdc import *
3
4 from lib.sata.k7sataphy.std import *
5
6 class _PulseSynchronizer(PulseSynchronizer):
7 def __init__(self, i, idomain, o, odomain):
8 PulseSynchronizer.__init__(self, idomain, odomain)
9 self.comb += [
10 self.i.eq(i),
11 o.eq(self.o)
12 ]
13
14 class K7SATAPHYGTX(Module):
15 def __init__(self, pads, default_speed):
16 # Interface
17 self.drp = DRPBus()
18
19 # Channel - Ref Clock Ports
20 self.gtrefclk0 = Signal()
21
22 # Channel PLL
23 self.cplllock = Signal()
24 self.cpllreset = Signal()
25
26 # Receive Ports
27 self.rxuserrdy = Signal()
28 self.rxalign = Signal()
29
30 # Receive Ports - 8b10b Decoder
31 self.rxcharisk = Signal(2)
32 self.rxdisperr = Signal(2)
33
34 # Receive Ports - RX Data Path interface
35 self.gtrxreset = Signal()
36 self.rxdata = Signal(16)
37 self.rxoutclk = Signal()
38 self.rxusrclk = Signal()
39 self.rxusrclk2 = Signal()
40
41 # Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
42 self.rxelecidle = Signal()
43
44 # Receive Ports - RX Elastic Buffer and Phase Alignment Ports
45 self.rxdlyen = Signal()
46 self.rxdlysreset = Signal()
47 self.rxdlysresetdone = Signal()
48 self.rxphalign = Signal()
49 self.rxphaligndone = Signal()
50 self.rxphalignen = Signal()
51 self.rxphdlyreset = Signal()
52
53 # Receive Ports - RX PLL Ports
54 self.rxresetdone = Signal()
55
56 # Receive Ports - RX Ports for SATA
57 self.rxcominitdet = Signal()
58 self.rxcomwakedet = Signal()
59
60 # Transmit Ports
61 self.txuserrdy = Signal()
62
63 # Transmit Ports - 8b10b Encoder Control Ports
64 self.txcharisk = Signal(2)
65
66 # Transmit Ports - TX Buffer and Phase Alignment Ports
67 self.txdlyen = Signal()
68 self.txdlysreset = Signal()
69 self.txdlysresetdone = Signal()
70 self.txphalign = Signal()
71 self.txphaligndone = Signal()
72 self.txphalignen = Signal()
73 self.txphdlyreset = Signal()
74 self.txphinit = Signal()
75 self.txphinitdone = Signal()
76
77 # Transmit Ports - TX Data Path interface
78 self.gttxreset = Signal()
79 self.txdata = Signal(16)
80 self.txoutclk = Signal()
81 self.txusrclk = Signal()
82 self.txusrclk2 = Signal()
83
84 # Transmit Ports - TX PLL Ports
85 self.txresetdone = Signal()
86
87 # Transmit Ports - TX Ports for PCI Express
88 self.txelecidle = Signal(reset=1)
89
90 # Transmit Ports - TX Ports for SATA
91 self.txcomfinish = Signal()
92 self.txcominit = Signal()
93 self.txcomwake = Signal()
94 self.rxrate = Signal(3)
95 self.rxratedone = Signal()
96 self.txrate = Signal(3)
97 self.txratedone = Signal()
98
99 # Config at startup
100 div_config = {
101 "SATA1" : 4,
102 "SATA2" : 2,
103 "SATA3" : 1
104 }
105 rxout_div = div_config[default_speed]
106 txout_div = div_config[default_speed]
107
108 cdr_config = {
109 "SATA1" : 0x0380008BFF40100008,
110 "SATA2" : 0x0380008BFF40200008,
111 "SATA3" : 0X0380008BFF20200010
112 }
113 rxcdr_cfg = cdr_config[default_speed]
114
115 # Internals and clock domain crossing
116 # sys_clk --> sata_tx clk
117 txuserrdy = Signal()
118 txdlyen = Signal()
119 txdlysreset = Signal()
120 txphalign = Signal()
121 txphalignen = Signal()
122 txphdlyreset = Signal()
123 txphinit = Signal()
124 txelecidle = Signal(reset=1)
125 txcominit = Signal()
126 txcomwake = Signal()
127 txrate = Signal(3)
128
129 self.specials += [
130 MultiReg(self.txuserrdy, txuserrdy, "sata_tx"),
131 MultiReg(self.txdlyen, txdlyen, "sata_tx"),
132 MultiReg(self.txdlysreset, txdlysreset, "sata_tx"),
133 MultiReg(self.txphalign, txphalign, "sata_tx"),
134 MultiReg(self.txphalignen, txphalignen, "sata_tx"),
135 MultiReg(self.txphdlyreset, txphdlyreset, "sata_tx"),
136 MultiReg(self.txelecidle, txelecidle, "sata_tx"),
137 MultiReg(self.txrate, txrate, "sata_tx")
138 ]
139 self.submodules += [
140 _PulseSynchronizer(self.txcominit, "sys", txcominit, "sata_tx"),
141 _PulseSynchronizer(self.txcomwake, "sys", txcomwake, "sata_tx"),
142 ]
143
144 # sata_tx clk --> sys clk
145 txdlysresetdone = Signal()
146 txphaligndone = Signal()
147 txphinitdone = Signal()
148 txresetdone = Signal()
149 txratedone = Signal()
150 txcomfinish = Signal()
151
152 self.specials += [
153 MultiReg(txdlysresetdone, self.txdlysresetdone, "sys"),
154 MultiReg(txphaligndone, self.txphaligndone, "sys"),
155 MultiReg(txphinitdone, self.txphinitdone, "sys"),
156 MultiReg(txresetdone, self.txresetdone, "sys"),
157 MultiReg(txratedone, self.txratedone, "sys"),
158 ]
159
160 self.submodules += [
161 _PulseSynchronizer(txcomfinish, "sata_tx", self.txcomfinish, "sys"),
162 ]
163
164 # sys clk --> sata_rx clk
165 rxuserrdy = Signal()
166 rxelecidle = Signal()
167 rxdlyen = Signal()
168 rxdlysreset = Signal()
169 rxphalign = Signal()
170 rxphalignen = Signal()
171 rxphdlyreset = Signal()
172 rxrate = Signal(3)
173 rxalign = Signal()
174
175 self.specials += [
176 MultiReg(self.rxuserrdy, rxuserrdy, "sata_rx"),
177 MultiReg(self.rxelecidle, rxelecidle, "sata_rx"),
178 MultiReg(self.rxdlyen, rxdlyen, "sata_rx"),
179 MultiReg(self.rxdlysreset, rxdlysreset, "sata_rx"),
180 MultiReg(self.rxphalign, rxphalign, "sata_rx"),
181 MultiReg(self.rxphalignen, rxphalignen, "sata_rx"),
182 MultiReg(self.rxphdlyreset, rxphdlyreset, "sata_rx"),
183 MultiReg(self.rxrate, rxrate, "sata_rx"),
184 MultiReg(self.rxalign, rxalign, "sata_rx"),
185 ]
186
187
188 # sata_rx clk --> sys clk
189 rxdlysresetdone = Signal()
190 rxphaligndone = Signal()
191 rxresetdone = Signal()
192 rxcominitdet = Signal()
193 rxcomwakedet = Signal()
194 rxratedone = Signal()
195
196 self.specials += [
197 MultiReg(rxdlysresetdone, self.rxdlysresetdone, "sys"),
198 MultiReg(rxphaligndone, self.rxphaligndone, "sys"),
199 MultiReg(rxresetdone, self.rxresetdone, "sys"),
200 MultiReg(rxratedone, self.rxratedone, "sys")
201 ]
202
203 self.submodules += [
204 _PulseSynchronizer(rxcominitdet, "sata_rx", self.rxcominitdet, "sys"),
205 _PulseSynchronizer(rxcomwakedet, "sata_rx", self.rxcomwakedet, "sys"),
206 ]
207
208
209 self.rxbyteisaligned = Signal()
210 self.rxbyterealign = Signal()
211 self.rxcommadet = Signal()
212
213 # Bypass TX buffer
214 self.comb += [
215 self.txphdlyreset.eq(0),
216 self.txphalignen.eq(0),
217 self.txdlyen.eq(0),
218 self.txphalign.eq(0),
219 self.txphinit.eq(0)
220 ]
221
222 # Bypass RX buffer
223 self.comb += [
224 self.rxphdlyreset.eq(0),
225 self.rxdlyen.eq(0),
226 self.rxphalign.eq(0),
227 self.rxphalignen.eq(0),
228 ]
229
230 # QPLL input clock
231 self.qpllclk = Signal()
232 self.qpllrefclk = Signal()
233
234 # Instance
235 gtxe2_channel_parameters = {
236 # Simulation-Only Attributes
237 "p_SIM_RECEIVER_DETECT_PASS":"TRUE",
238 "p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
239 "p_SIM_RESET_SPEEDUP":"TRUE",
240 "p_SIM_CPLLREFCLK_SEL":0b001,
241 "p_SIM_VERSION":"4.0",
242
243 # RX Byte and Word Alignment Attributes
244 "p_ALIGN_COMMA_DOUBLE":"FALSE",
245 "p_ALIGN_COMMA_ENABLE":ones(10),
246 "p_ALIGN_COMMA_WORD":2,
247 "p_ALIGN_MCOMMA_DET":"TRUE",
248 "p_ALIGN_MCOMMA_VALUE":0b1010000011,
249 "p_ALIGN_PCOMMA_DET":"TRUE",
250 "p_ALIGN_PCOMMA_VALUE":0b0101111100,
251 "p_SHOW_REALIGN_COMMA":"FALSE",
252 "p_RXSLIDE_AUTO_WAIT":7,
253 "p_RXSLIDE_MODE":"OFF",
254 "p_RX_SIG_VALID_DLY":10,
255
256 # RX 8B/10B Decoder Attributes
257 "p_RX_DISPERR_SEQ_MATCH":"TRUE",
258 "p_DEC_MCOMMA_DETECT":"TRUE",
259 "p_DEC_PCOMMA_DETECT":"TRUE",
260 "p_DEC_VALID_COMMA_ONLY":"TRUE",
261
262 # RX Clock Correction Attributes
263 "p_CBCC_DATA_SOURCE_SEL":"DECODED",
264 "p_CLK_COR_SEQ_2_USE":"FALSE",
265 "p_CLK_COR_KEEP_IDLE":"FALSE",
266 "p_CLK_COR_MAX_LAT":9,
267 "p_CLK_COR_MIN_LAT":7,
268 "p_CLK_COR_PRECEDENCE":"TRUE",
269 "p_CLK_COR_REPEAT_WAIT":0,
270 "p_CLK_COR_SEQ_LEN":1,
271 "p_CLK_COR_SEQ_1_ENABLE":ones(4),
272 "p_CLK_COR_SEQ_1_ENABLE":0,
273 "p_CLK_COR_SEQ_1_1":0,
274 "p_CLK_COR_SEQ_1_1":0,
275 "p_CLK_COR_SEQ_1_2":0,
276 "p_CLK_COR_SEQ_1_3":0,
277 "p_CLK_COR_SEQ_1_4":0,
278 "p_CLK_CORRECT_USE":"FALSE",
279 "p_CLK_COR_SEQ_2_ENABLE":ones(4),
280 "p_CLK_COR_SEQ_2_1":0,
281 "p_CLK_COR_SEQ_2_2":0,
282 "p_CLK_COR_SEQ_2_3":0,
283 "p_CLK_COR_SEQ_2_4":0,
284
285 # RX Channel Bonding Attributes
286 "p_CHAN_BOND_KEEP_ALIGN":"FALSE",
287 "p_CHAN_BOND_MAX_SKEW":1,
288 "p_CHAN_BOND_SEQ_LEN":1,
289 "p_CHAN_BOND_SEQ_1_1":0,
290 "p_CHAN_BOND_SEQ_1_1":0,
291 "p_CHAN_BOND_SEQ_1_2":0,
292 "p_CHAN_BOND_SEQ_1_3":0,
293 "p_CHAN_BOND_SEQ_1_4":0,
294 "p_CHAN_BOND_SEQ_1_ENABLE":ones(4),
295 "p_CHAN_BOND_SEQ_2_1":0,
296 "p_CHAN_BOND_SEQ_2_2":0,
297 "p_CHAN_BOND_SEQ_2_3":0,
298 "p_CHAN_BOND_SEQ_2_4":0,
299 "p_CHAN_BOND_SEQ_2_ENABLE":ones(4),
300 "p_CHAN_BOND_SEQ_2_USE":"FALSE",
301 "p_FTS_DESKEW_SEQ_ENABLE":ones(4),
302 "p_FTS_LANE_DESKEW_CFG":ones(4),
303 "p_FTS_LANE_DESKEW_EN":"FALSE",
304
305 # RX Margin Analysis Attributes
306 "p_ES_CONTROL":0,
307 "p_ES_ERRDET_EN":"FALSE",
308 "p_ES_EYE_SCAN_EN":"TRUE",
309 "p_ES_HORZ_OFFSET":0,
310 "p_ES_PMA_CFG":0,
311 "p_ES_PRESCALE":0,
312 "p_ES_QUALIFIER":0,
313 "p_ES_QUAL_MASK":0,
314 "p_ES_SDATA_MASK":0,
315 "p_ES_VERT_OFFSET":0,
316
317 # FPGA RX Interface Attributes
318 "p_RX_DATA_WIDTH":20,
319
320 # PMA Attributes
321 "p_OUTREFCLK_SEL_INV":0b11,
322 "p_PMA_RSV":0x00018480,
323 "p_PMA_RSV2":0x2050,
324 "p_PMA_RSV3":0,
325 "p_PMA_RSV4":0,
326 "p_RX_BIAS_CFG":0b100,
327 "p_DMONITOR_CFG":0xA00,
328 "p_RX_CM_SEL":0b11,
329 "p_RX_CM_TRIM":0b010,
330 "p_RX_DEBUG_CFG":0,
331 "p_RX_OS_CFG":0b10000000,
332 "p_TERM_RCAL_CFG":0,
333 "p_TERM_RCAL_OVRD":0,
334 "p_TST_RSV":0,
335 "p_RX_CLK25_DIV":6,
336 "p_TX_CLK25_DIV":6,
337 "p_UCODEER_CLR":0,
338
339 # PCI Express Attributes
340 "p_PCS_PCIE_EN":"FALSE",
341
342 # PCS Attributes
343 "p_PCS_RSVD_ATTR":0x100,
344
345 # RX Buffer Attributes
346 "p_RXBUF_ADDR_MODE":"FAST",
347 "p_RXBUF_EIDLE_HI_CNT":0b1000,
348 "p_RXBUF_EIDLE_LO_CNT":0,
349 "p_RXBUF_EN":"FALSE",
350 "p_RX_BUFFER_CFG":0,
351 "p_RXBUF_RESET_ON_CB_CHANGE":"TRUE",
352 "p_RXBUF_RESET_ON_COMMAALIGN":"FALSE",
353 "p_RXBUF_RESET_ON_EIDLE":"FALSE",
354 "p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE",
355 "p_RXBUFRESET_TIME":1,
356 "p_RXBUF_THRESH_OVFLW":61,
357 "p_RXBUF_THRESH_OVRD":"FALSE",
358 "p_RXBUF_THRESH_UNDFLW":4,
359 "p_RXDLY_CFG":0x1f,
360 "p_RXDLY_LCFG":0x30,
361 "p_RXDLY_TAP_CFG":0,
362 "p_RXPH_CFG":0,
363 "p_RXPHDLY_CFG":0x084820,
364 "p_RXPH_MONITOR_SEL":0,
365 "p_RX_XCLK_SEL":"RXUSR",
366 "p_RX_DDI_SEL":0,
367 "p_RX_DEFER_RESET_BUF_EN":"TRUE",
368
369 #CDR Attributes
370 "p_RXCDR_CFG":rxcdr_cfg,
371 "p_RXCDR_FR_RESET_ON_EIDLE":0,
372 "p_RXCDR_HOLD_DURING_EIDLE":0,
373 "p_RXCDR_PH_RESET_ON_EIDLE":0,
374 "p_RXCDR_LOCK_CFG":0b010101,
375
376 # RX Initialization and Reset Attributes
377 "p_RXCDRFREQRESET_TIME":1,
378 "p_RXCDRPHRESET_TIME":1,
379 "p_RXISCANRESET_TIME":1,
380 "p_RXPCSRESET_TIME":1,
381 "p_RXPMARESET_TIME":3,
382
383 # RX OOB Signaling Attributes
384 "p_RXOOB_CFG":0b0000110,
385
386 # RX Gearbox Attributes
387 "p_RXGEARBOX_EN":"FALSE",
388 "p_GEARBOX_MODE":0,
389
390 # PRBS Detection Attribute
391 "p_RXPRBS_ERR_LOOPBACK":0,
392
393 # Power-Down Attributes
394 "p_PD_TRANS_TIME_FROM_P2":0x03c,
395 "p_PD_TRANS_TIME_NONE_P2":0x3c,
396 "p_PD_TRANS_TIME_TO_P2":0x64,
397
398 # RX OOB Signaling Attributes
399 "p_SAS_MAX_COM":64,
400 "p_SAS_MIN_COM":36,
401 "p_SATA_BURST_SEQ_LEN":0b0101,
402 "p_SATA_BURST_VAL":0b100,
403 "p_SATA_EIDLE_VAL":0b100,
404 "p_SATA_MAX_BURST":8,
405 "p_SATA_MAX_INIT":21,
406 "p_SATA_MAX_WAKE":7,
407 "p_SATA_MIN_BURST":4,
408 "p_SATA_MIN_INIT":12,
409 "p_SATA_MIN_WAKE":4,
410
411 # RX Fabric Clock Output Control Attributes
412 "p_TRANS_TIME_RATE":0x0e,
413
414 # TX Buffer Attributes
415 "p_TXBUF_EN":"FALSE",
416 "p_TXBUF_RESET_ON_RATE_CHANGE":"FALSE",
417 "p_TXDLY_CFG":0x1f,
418 "p_TXDLY_LCFG":0x030,
419 "p_TXDLY_TAP_CFG":0,
420 "p_TXPH_CFG":0x0780,
421 "p_TXPHDLY_CFG":0x084020,
422 "p_TXPH_MONITOR_SEL":0,
423 "p_TX_XCLK_SEL":"TXUSR",
424
425 # FPGA TX Interface Attributes
426 "p_TX_DATA_WIDTH":20,
427
428 # TX Configurable Driver Attributes
429 "p_TX_DEEMPH0":0,
430 "p_TX_DEEMPH1":0,
431 "p_TX_EIDLE_ASSERT_DELAY":0b110,
432 "p_TX_EIDLE_DEASSERT_DELAY":0b100,
433 "p_TX_LOOPBACK_DRIVE_HIZ":"FALSE",
434 "p_TX_MAINCURSOR_SEL":0,
435 "p_TX_DRIVE_MODE":"DIRECT",
436 "p_TX_MARGIN_FULL_0":0b1001110,
437 "p_TX_MARGIN_FULL_1":0b1001001,
438 "p_TX_MARGIN_FULL_2":0b1000101,
439 "p_TX_MARGIN_FULL_3":0b1000010,
440 "p_TX_MARGIN_FULL_4":0b1000000,
441 "p_TX_MARGIN_LOW_0":0b1000110,
442 "p_TX_MARGIN_LOW_1":0b1000100,
443 "p_TX_MARGIN_LOW_2":0b1000010,
444 "p_TX_MARGIN_LOW_3":0b1000000,
445 "p_TX_MARGIN_LOW_4":0b1000000,
446
447 # TX Gearbox Attributes
448 "p_TXGEARBOX_EN":"FALSE",
449
450 # TX Initialization and Reset Attributes
451 "p_TXPCSRESET_TIME":1,
452 "p_TXPMARESET_TIME":1,
453
454 # TX Receiver Detection Attributes
455 "p_TX_RXDETECT_CFG":0x1832,
456 "p_TX_RXDETECT_REF":0b100,
457
458 # CPLL Attributes
459 "p_CPLL_CFG":0xBC07DC,
460 "p_CPLL_FBDIV":4,
461 "p_CPLL_FBDIV_45":5,
462 "p_CPLL_INIT_CFG":0x00001e,
463 "p_CPLL_LOCK_CFG":0x01e8,
464 "p_CPLL_REFCLK_DIV":1,
465 "p_RXOUT_DIV":rxout_div,
466 "p_TXOUT_DIV":txout_div,
467 "p_SATA_CPLL_CFG":"VCO_3000MHZ",
468
469 # RX Initialization and Reset Attributes
470 "p_RXDFELPMRESET_TIME":0b0001111,
471
472 # RX Equalizer Attributes
473 "p_RXLPM_HF_CFG":0b00000011110000,
474 "p_RXLPM_LF_CFG":0b00000011110000,
475 "p_RX_DFE_GAIN_CFG":0x020fea,
476 "p_RX_DFE_H2_CFG":0b000000000000,
477 "p_RX_DFE_H3_CFG":0b000001000000,
478 "p_RX_DFE_H4_CFG":0b00011110000,
479 "p_RX_DFE_H5_CFG":0b00011100000,
480 "p_RX_DFE_KL_CFG":0b0000011111110,
481 "p_RX_DFE_LPM_CFG":0x0954,
482 "p_RX_DFE_LPM_HOLD_DURING_EIDLE":1,
483 "p_RX_DFE_UT_CFG":0b10001111000000000,
484 "p_RX_DFE_VP_CFG":0b00011111100000011,
485
486 # Power-Down Attributes
487 "p_RX_CLKMUX_PD":1,
488 "p_TX_CLKMUX_PD":1,
489
490 # FPGA RX Interface Attribute
491 "p_RX_INT_DATAWIDTH":0,
492
493 # FPGA TX Interface Attribute
494 "p_TX_INT_DATAWIDTH":0,
495
496 # TX Configurable Driver Attributes
497 "p_TX_QPI_STATUS_EN":0,
498
499 # RX Equalizer Attributes
500 "p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100,
501 "p_RX_DFE_XYD_CFG":0b0000000000000,
502
503 # TX Configurable Driver Attributes
504 "p_TX_PREDRIVER_MODE":0,
505 }
506
507 self.specials += \
508 Instance("GTXE2_CHANNEL",
509 # CPLL Ports
510 #o_CPLLFBCLKLOST=,
511 o_CPLLLOCK=self.cplllock,
512 i_CPLLLOCKDETCLK=0,
513 i_CPLLLOCKEN=1,
514 i_CPLLPD=0,
515 #o_CPLLREFCLKLOST=0,
516 i_CPLLREFCLKSEL=0b001,
517 i_CPLLRESET=self.cpllreset,
518 i_GTRSVD=0,
519 i_PCSRSVDIN=0,
520 i_PCSRSVDIN2=0,
521 i_PMARSVDIN=0,
522 i_PMARSVDIN2=0,
523 i_TSTIN=ones(20),
524 #o_TSTOUT=,
525
526 # Channel
527 i_CLKRSVD=0,
528
529 # Channel - Clocking Ports
530 i_GTGREFCLK=0,
531 i_GTNORTHREFCLK0=0,
532 i_GTNORTHREFCLK1=0,
533 i_GTREFCLK0=self.gtrefclk0,
534 i_GTREFCLK1=0,
535 i_GTSOUTHREFCLK0=0,
536 i_GTSOUTHREFCLK1=0,
537
538 # Channel - DRP Ports
539 i_DRPADDR=self.drp.addr,
540 i_DRPCLK=self.drp.clk,
541 i_DRPDI=self.drp.di,
542 o_DRPDO=self.drp.do,
543 i_DRPEN=self.drp.en,
544 o_DRPRDY=self.drp.rdy,
545 i_DRPWE=self.drp.we,
546
547 # Clocking Ports
548 #o_GTREFCLKMONITOR=,
549 i_QPLLCLK=self.qpllclk,
550 i_QPLLREFCLK=self.qpllrefclk,
551 i_RXSYSCLKSEL=0b00,
552 i_TXSYSCLKSEL=0b00,
553
554 # Digital Monitor Ports
555 #o_DMONITOROUT=,
556
557 # FPGA TX Interface Datapath Configuration
558 i_TX8B10BEN=1,
559
560 # Loopback Ports
561 i_LOOPBACK=0,
562
563 # PCI Express Ports
564 #o_PHYSTATUS=,
565 i_RXRATE=rxrate,
566 #o_RXVALID=,
567
568 # Power-Down Ports
569 i_RXPD=0b00,
570 i_TXPD=0b00,
571
572 # RX 8B/10B Decoder Ports
573 i_SETERRSTATUS=0,
574
575 # RX Initialization and Reset Ports
576 i_EYESCANRESET=0,
577 i_RXUSERRDY=rxuserrdy,
578
579 # RX Margin Analysis Ports
580 #o_EYESCANDATAERROR=,
581 i_EYESCANMODE=0,
582 i_EYESCANTRIGGER=0,
583
584 # Receive Ports - CDR Ports
585 i_RXCDRFREQRESET=0,
586 i_RXCDRHOLD=0,
587 #o_RXCDRLOCK=,
588 i_RXCDROVRDEN=0,
589 i_RXCDRRESET=0,
590 i_RXCDRRESETRSV=0,
591
592 # Receive Ports - Clock Correction Ports
593 #o_RXCLKCORCNT=,
594
595 # Receive Ports - FPGA RX Interface Datapath Configuration
596 i_RX8B10BEN=1,
597
598 # Receive Ports - FPGA RX Interface Ports
599 i_RXUSRCLK=self.rxusrclk,
600 i_RXUSRCLK2=self.rxusrclk2,
601
602 # Receive Ports - FPGA RX interface Ports
603 o_RXDATA=self.rxdata,
604
605 # Receive Ports - Pattern Checker Ports
606 #o_RXPRBSERR=,
607 i_RXPRBSSEL=0,
608
609 # Receive Ports - Pattern Checker ports
610 i_RXPRBSCNTRESET=0,
611
612 # Receive Ports - RX Equalizer Ports
613 i_RXDFEXYDEN=0,
614 i_RXDFEXYDHOLD=0,
615 i_RXDFEXYDOVRDEN=0,
616
617 # Receive Ports - RX 8B/10B Decoder Ports
618 #o_RXDISPERR=,
619 #o_RXNOTINTABLE=,
620
621 # Receive Ports - RX AFE
622 i_GTXRXP=pads.rxp,
623 i_GTXRXN=pads.rxn,
624
625 # Receive Ports - RX Buffer Bypass Ports
626 i_RXBUFRESET=0,
627 #o_RXBUFSTATUS=,
628 i_RXDDIEN=1,
629 i_RXDLYBYPASS=0,
630 i_RXDLYEN=rxdlyen,
631 i_RXDLYOVRDEN=0,
632 i_RXDLYSRESET=rxdlysreset,
633 o_RXDLYSRESETDONE=rxdlysresetdone,
634 i_RXPHALIGN=rxphalign,
635 o_RXPHALIGNDONE=rxphaligndone,
636 i_RXPHALIGNEN=rxphalignen,
637 i_RXPHDLYPD=0,
638 i_RXPHDLYRESET=rxphdlyreset,
639 #o_RXPHMONITOR=,
640 i_RXPHOVRDEN=0,
641 #o_RXPHSLIPMONITOR=,
642 #o_RXSTATUS=,
643
644 # Receive Ports - RX Byte and Word Alignment Ports
645 o_RXBYTEISALIGNED=self.rxbyteisaligned,
646 o_RXBYTEREALIGN=self.rxbyterealign,
647 o_RXCOMMADET=self.rxcommadet,
648 i_RXCOMMADETEN=1,
649 i_RXMCOMMAALIGNEN=rxalign,
650 i_RXPCOMMAALIGNEN=rxalign,
651
652 # Receive Ports - RX Channel Bonding Ports
653 #o_RXCHANBONDSEQ=,
654 i_RXCHBONDEN=0,
655 i_RXCHBONDLEVEL=0,
656 i_RXCHBONDMASTER=0,
657 #o_RXCHBONDO=,
658 i_RXCHBONDSLAVE=0,
659
660 # Receive Ports - RX Channel Bonding Ports
661 #o_RXCHANISALIGNED=,
662 #o_RXCHANREALIGN=,
663
664 # Receive Ports - RX Equalizer Ports
665 i_RXDFEAGCHOLD=0,
666 i_RXDFEAGCOVRDEN=0,
667 i_RXDFECM1EN=0,
668 i_RXDFELFHOLD=0,
669 i_RXDFELFOVRDEN=1,
670 i_RXDFELPMRESET=0,
671 i_RXDFETAP2HOLD=0,
672 i_RXDFETAP2OVRDEN=0,
673 i_RXDFETAP3HOLD=0,
674 i_RXDFETAP3OVRDEN=0,
675 i_RXDFETAP4HOLD=0,
676 i_RXDFETAP4OVRDEN=0,
677 i_RXDFETAP5HOLD=0,
678 i_RXDFETAP5OVRDEN=0,
679 i_RXDFEUTHOLD=0,
680 i_RXDFEUTOVRDEN=0,
681 i_RXDFEVPHOLD=0,
682 i_RXDFEVPOVRDEN=0,
683 i_RXDFEVSEN=0,
684 i_RXLPMLFKLOVRDEN=0,
685 #o_RXMONITOROUT=,
686 i_RXMONITORSEL=0b00,
687 i_RXOSHOLD=0,
688 i_RXOSOVRDEN=0,
689
690 # Receive Ports - RX Equilizer Ports
691 i_RXLPMHFHOLD=0,
692 i_RXLPMHFOVRDEN=0,
693 i_RXLPMLFHOLD=0,
694
695 # Receive Ports - RX Fabric ClocK Output Control Ports
696 o_RXRATEDONE=rxratedone,
697
698 # Receive Ports - RX Fabric Output Control Ports
699 o_RXOUTCLK=self.rxoutclk,
700 #o_RXOUTCLKFABRIC=,
701 #o_RXOUTCLKPCS=,
702 i_RXOUTCLKSEL=0b010,
703
704 # Receive Ports - RX Gearbox Ports
705 #o_RXDATAVALID=,
706 #o_RXHEADER=,
707 #o_RXHEADERVALID=,
708 #o_RXSTARTOFSEQ=,
709
710 # Receive Ports - RX Gearbox Ports
711 i_RXGEARBOXSLIP=0,
712
713 # Receive Ports - RX Initialization and Reset Ports
714 i_GTRXRESET=self.gtrxreset,
715 i_RXOOBRESET=0,
716 i_RXPCSRESET=0,
717 i_RXPMARESET=0,
718
719 # Receive Ports - RX Margin Analysis ports
720 i_RXLPMEN=0,
721
722 # Receive Ports - RX OOB Signaling ports
723 #o_RXCOMSASDET=,
724 o_RXCOMWAKEDET=rxcomwakedet,
725
726 # Receive Ports - RX OOB Signaling ports
727 o_RXCOMINITDET=rxcominitdet,
728
729 # Receive Ports - RX OOB signalling Ports
730 o_RXELECIDLE=rxelecidle,
731 i_RXELECIDLEMODE=0b00,
732
733 # Receive Ports - RX Polarity Control Ports
734 i_RXPOLARITY=0,
735
736 # Receive Ports - RX gearbox ports
737 i_RXSLIDE=0,
738
739 # Receive Ports - RX8B/10B Decoder Ports
740 #o_RXCHARISCOMMA=,
741 o_RXCHARISK=self.rxcharisk,
742
743 # Receive Ports - Rx Channel Bonding Ports
744 i_RXCHBONDI=0,
745
746 # Receive Ports -RX Initialization and Reset Ports
747 o_RXRESETDONE=rxresetdone,
748
749 # Rx AFE Ports
750 i_RXQPIEN=0,
751 #o_RXQPISENN=,
752 #o_RXQPISENP=,
753
754 # TX Buffer Bypass Ports
755 i_TXPHDLYTSTCLK=0,
756
757 # TX Configurable Driver Ports
758 i_TXPOSTCURSOR=0,
759 i_TXPOSTCURSORINV=0,
760 i_TXPRECURSOR=0,
761 i_TXPRECURSORINV=0,
762 i_TXQPIBIASEN=0,
763 i_TXQPISTRONGPDOWN=0,
764 i_TXQPIWEAKPUP=0,
765
766 # TX Initialization and Reset Ports
767 i_CFGRESET=0,
768 i_GTTXRESET=self.gttxreset,
769 #o_PCSRSVDOUT=,
770 i_TXUSERRDY=txuserrdy,
771
772 # Transceiver Reset Mode Operation
773 i_GTRESETSEL=0,
774 i_RESETOVRD=0,
775
776 # Transmit Ports - 8b10b Encoder Control Ports
777 i_TXCHARDISPMODE=0,
778 i_TXCHARDISPVAL=0,
779
780 # Transmit Ports - FPGA TX Interface Ports
781 i_TXUSRCLK=self.txusrclk,
782 i_TXUSRCLK2=self.txusrclk2,
783
784 # Transmit Ports - PCI Express Ports
785 i_TXELECIDLE=txelecidle,
786 i_TXMARGIN=0,
787 i_TXRATE=txrate,
788 i_TXSWING=0,
789
790 # Transmit Ports - Pattern Generator Ports
791 i_TXPRBSFORCEERR=0,
792
793 # Transmit Ports - TX Buffer Bypass Ports
794 i_TXDLYBYPASS=0,
795 i_TXDLYEN=txdlyen,
796 i_TXDLYHOLD=0,
797 i_TXDLYOVRDEN=0,
798 i_TXDLYSRESET=txdlysreset,
799 o_TXDLYSRESETDONE=txdlysresetdone,
800 i_TXDLYUPDOWN=0,
801 i_TXPHALIGN=txphalign,
802 o_TXPHALIGNDONE=txphaligndone,
803 i_TXPHALIGNEN=txphalignen,
804 i_TXPHDLYPD=0,
805 i_TXPHDLYRESET=txphdlyreset,
806 i_TXPHINIT=txphinit,
807 o_TXPHINITDONE=txphinitdone,
808 i_TXPHOVRDEN=0,
809
810 # Transmit Ports - TX Buffer Ports
811 #o_TXBUFSTATUS=,
812
813 # Transmit Ports - TX Configurable Driver Ports
814 i_TXBUFDIFFCTRL=0b100,
815 i_TXDEEMPH=0,
816 i_TXDIFFCTRL=0b1000,
817 i_TXDIFFPD=0,
818 i_TXINHIBIT=0,
819 i_TXMAINCURSOR=0,
820 i_TXPISOPD=0,
821
822 # Transmit Ports - TX Data Path interface
823 i_TXDATA=self.txdata,
824
825 # Transmit Ports - TX Driver and OOB signaling
826 o_GTXTXP=pads.txp,
827 o_GTXTXN=pads.txn,
828
829 # Transmit Ports - TX Fabric Clock Output Control Ports
830 o_TXOUTCLK=self.txoutclk,
831 #o_TXOUTCLKFABRIC=,
832 #o_TXOUTCLKPCS=,
833 i_TXOUTCLKSEL=0b11,
834 o_TXRATEDONE=txratedone,
835 # Transmit Ports - TX Gearbox Ports
836 i_TXCHARISK=self.txcharisk,
837 #o_TXGEARBOXREADY=,
838 i_TXHEADER=0,
839 i_TXSEQUENCE=0,
840 i_TXSTARTSEQ=0,
841
842 # Transmit Ports - TX Initialization and Reset Ports
843 i_TXPCSRESET=0,
844 i_TXPMARESET=0,
845 o_TXRESETDONE=txresetdone,
846
847 # Transmit Ports - TX OOB signalling Ports
848 o_TXCOMFINISH=txcomfinish,
849 i_TXCOMINIT=txcominit,
850 i_TXCOMSAS=0,
851 i_TXCOMWAKE=txcomwake,
852 i_TXPDELECIDLEMODE=0,
853
854 # Transmit Ports - TX Polarity Control Ports
855 i_TXPOLARITY=0,
856
857 # Transmit Ports - TX Receiver Detection Ports
858 i_TXDETECTRX=0,
859
860 # Transmit Ports - TX8b/10b Encoder Ports
861 i_TX8B10BBYPASS=0,
862
863 # Transmit Ports - pattern Generator Ports
864 i_TXPRBSSEL=0,
865
866 # Tx Configurable Driver Ports
867 #o_TXQPISENN=,
868 #o_TXQPISENP=,
869
870 **gtxe2_channel_parameters
871 )
872
873
874 class GTXE2_COMMON(Module):
875 def __init__(self, fbdiv=16):
876 self.refclk0 = Signal()
877
878 self.qpllclk = Signal()
879 self.qpllrefclk = Signal()
880
881 # fbdiv config
882 fbdiv_in_config = {
883 16 : 0b0000100000,
884 20 : 0b0000110000,
885 32 : 0b0001100000,
886 40 : 0b0010000000,
887 64 : 0b0011100000,
888 66 : 0b0101000000,
889 80 : 0b0100100000,
890 100 : 0b0101110000
891 }
892 fbdiv_in = fbdiv_in_config[fbdiv]
893
894 fbdiv_ratio_config = {
895 16 : 0b1,
896 20 : 0b1,
897 32 : 0b1,
898 40 : 0b1,
899 64 : 0b1,
900 66 : 0b0,
901 80 : 0b1,
902 100 : 0b1
903 }
904 fbdiv_ratio = fbdiv_ratio_config[fbdiv]
905
906 self.specials += \
907 Instance("GTXE2_COMMON",
908 # Simulation attributes
909 p_SIM_RESET_SPEEDUP="TRUE",
910 p_SIM_QPLLREFCLK_SEL=0b001,
911 p_SIM_VERSION="4.0",
912
913 # Common block attributes
914 p_BIAS_CFG=0x0000040000001000,
915 p_COMMON_CFG=0,
916 p_QPLL_CFG=0x06801c1,
917 p_QPLL_CLKOUT_CFG=0,
918 p_QPLL_COARSE_FREQ_OVRD=0b010000,
919 p_QPLL_COARSE_FREQ_OVRD_EN=0,
920 p_QPLL_CP=0b0000011111,
921 p_QPLL_CP_MONITOR_EN=0,
922 p_QPLL_DMONITOR_SEL=0,
923 p_QPLL_FBDIV=fbdiv_in,
924 p_QPLL_FBDIV_MONITOR_EN=0,
925 p_QPLL_FBDIV_RATIO=fbdiv_ratio,
926 p_QPLL_INIT_CFG=0x000006,
927 p_QPLL_LOCK_CFG=0x21e9,
928 p_QPLL_LPF=0b1111,
929 p_QPLL_REFCLK_DIV=1,
930
931 # Common block - Dynamic Reconfiguration Port (DRP)
932 i_DRPADDR=0,
933 i_DRPCLK=0,
934 i_DRPDI=0,
935 #o_DRPDO=,
936 i_DRPEN=0,
937 #o_DRPRDY=,
938 i_DRPWE=0,
939
940 # Common block - Ref Clock Ports
941 i_GTGREFCLK=0,
942 i_GTNORTHREFCLK0=0,
943 i_GTNORTHREFCLK1=0,
944 i_GTREFCLK0=self.refclk0,
945 i_GTREFCLK1=0,
946 i_GTSOUTHREFCLK0=0,
947 i_GTSOUTHREFCLK1=0,
948
949 # Common block - QPLL Ports
950 #o_QPLLDMONITOR=,
951 #o_QPLLFBCLKLOST=,
952 #o_QPLLLOCK=,
953 i_QPLLLOCKDETCLK=0,
954 i_QPLLLOCKEN=1,
955 o_QPLLOUTCLK=self.qpllclk,
956 o_QPLLOUTREFCLK=self.qpllrefclk,
957 i_QPLLOUTRESET=0,
958 i_QPLLPD=0,
959 #o_QPLLREFCLKLOST=,
960 i_QPLLREFCLKSEL=0b001,
961 i_QPLLRESET=0,
962 i_QPLLRSVD1=0,
963 i_QPLLRSVD2=ones(5),
964 #o_REFCLKOUTMONITOR=,
965
966 # Common block Ports
967 i_BGBYPASSB=1,
968 i_BGMONITORENB=1,
969 i_BGPDB=1,
970 i_BGRCALOVRD=0,
971 i_PMARSVD=0,
972 i_RCALENB=1
973 )