1 from lib
.sata
.common
import *
3 from migen
.genlib
.cdc
import *
8 class _PulseSynchronizer(PulseSynchronizer
):
9 def __init__(self
, i
, idomain
, o
, odomain
):
10 PulseSynchronizer
.__init
__(self
, idomain
, odomain
)
16 class _RisingEdge(Module
):
17 def __init__(self
, i
, o
):
19 self
.sync
+= i_d
.eq(i
)
20 self
.comb
+= o
.eq(i
& ~i_d
)
22 class K7SATAPHYTRX(Module
):
23 def __init__(self
, pads
, speed
):
27 self
.tx_idle
= Signal() #i
29 self
.tx_cominit_stb
= Signal() #i
30 self
.tx_cominit_ack
= Signal() #o
31 self
.tx_comwake_stb
= Signal() #i
32 self
.tx_comwake_ack
= Signal() #o
34 self
.rx_idle
= Signal() #o
35 self
.rx_align
= Signal() #i
37 self
.rx_cominit_stb
= Signal() #o
38 self
.rx_comwake_stb
= Signal() #o
41 self
.sink
= Sink(phy_description(16))
42 self
.source
= Source(phy_description(16))
45 # Channel - Ref Clock Ports
46 self
.gtrefclk0
= Signal()
49 self
.cplllock
= Signal()
50 self
.cpllreset
= Signal()
53 self
.rxuserrdy
= Signal()
54 self
.rxalign
= Signal()
56 # Receive Ports - 8b10b Decoder
57 self
.rxcharisk
= Signal(2)
58 self
.rxdisperr
= Signal(2)
60 # Receive Ports - RX Data Path interface
61 self
.gtrxreset
= Signal()
62 self
.pmarxreset
= Signal()
63 self
.rxdata
= Signal(16)
64 self
.rxoutclk
= Signal()
65 self
.rxusrclk
= Signal()
66 self
.rxusrclk2
= Signal()
68 # Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
69 self
.rxelecidle
= Signal()
71 # Receive Ports - RX PLL Ports
72 self
.rxresetdone
= Signal()
74 # Receive Ports - RX Ports for SATA
75 self
.rxcominitdet
= Signal()
76 self
.rxcomwakedet
= Signal()
79 self
.txuserrdy
= Signal()
81 # Transmit Ports - 8b10b Encoder Control Ports
82 self
.txcharisk
= Signal(2)
84 # Transmit Ports - TX Data Path interface
85 self
.gttxreset
= Signal()
86 self
.txdata
= Signal(16)
87 self
.txoutclk
= Signal()
88 self
.txusrclk
= Signal()
89 self
.txusrclk2
= Signal()
91 # Transmit Ports - TX PLL Ports
92 self
.txresetdone
= Signal()
94 # Transmit Ports - TX Ports for PCI Express
95 self
.txelecidle
= Signal(reset
=1)
97 # Transmit Ports - TX Ports for SATA
98 self
.txcomfinish
= Signal()
99 self
.txcominit
= Signal()
100 self
.txcomwake
= Signal()
101 self
.txrate
= Signal(3)
102 self
.rxcdrlock
= Signal()
110 rxout_div
= div_config
[speed
]
111 txout_div
= div_config
[speed
]
114 "SATA1" : 0x0380008BFF40100008,
115 "SATA2" : 0x0388008BFF40200008,
116 "SATA3" : 0X0380008BFF10200010
118 rxcdr_cfg
= cdr_config
[speed
]
120 # Specific / Generic signals encoding/decoding
122 self
.txelecidle
.eq(self
.tx_idle
),
123 self
.tx_cominit_ack
.eq(self
.tx_cominit_stb
& self
.txcomfinish
),
124 self
.tx_comwake_ack
.eq(self
.tx_comwake_stb
& self
.txcomfinish
),
125 self
.rx_idle
.eq(self
.rxelecidle
),
126 self
.rxalign
.eq(self
.rx_align
),
127 self
.rx_cominit_stb
.eq(self
.rxcominitdet
),
128 self
.rx_comwake_stb
.eq(self
.rxcomwakedet
),
131 _RisingEdge(self
.tx_cominit_stb
, self
.txcominit
),
132 _RisingEdge(self
.tx_comwake_stb
, self
.txcomwake
),
136 self
.txcharisk
.eq(self
.sink
.charisk
),
137 self
.txdata
.eq(self
.sink
.data
),
140 self
.source
.stb
.eq(1),
141 self
.source
.charisk
.eq(self
.rxcharisk
),
142 self
.source
.data
.eq(self
.rxdata
)
145 # Internals and clock domain crossing
146 # sys_clk --> sata_tx clk
148 txelecidle
= Signal(reset
=1)
154 MultiReg(self
.txuserrdy
, txuserrdy
, "sata_tx"),
155 MultiReg(self
.txelecidle
, txelecidle
, "sata_tx"),
156 MultiReg(self
.txrate
, txrate
, "sata_tx")
159 _PulseSynchronizer(self
.txcominit
, "sys", txcominit
, "sata_tx"),
160 _PulseSynchronizer(self
.txcomwake
, "sys", txcomwake
, "sata_tx"),
163 # sata_tx clk --> sys clk
164 txresetdone
= Signal()
165 txcomfinish
= Signal()
168 MultiReg(txresetdone
, self
.txresetdone
, "sys"),
172 _PulseSynchronizer(txcomfinish
, "sata_tx", self
.txcomfinish
, "sys"),
175 # sys clk --> sata_rx clk
179 MultiReg(self
.rxuserrdy
, rxuserrdy
, "sata_rx"),
182 # sata_rx clk --> sys clk
183 rxelecidle
= Signal()
184 rxelecidle_i
= Signal()
185 rxelecidle_cnt_i
= Signal(9)
186 rxresetdone
= Signal()
187 rxcominitdet
= Signal()
188 rxcomwakedet
= Signal()
189 rxratedone
= Signal()
193 MultiReg(rxelecidle
, rxelecidle_i
, "sys"),
194 MultiReg(rxresetdone
, self
.rxresetdone
, "sys"),
195 MultiReg(rxcominitdet
, self
.rxcominitdet
, "sys"),
196 MultiReg(rxcomwakedet
, self
.rxcomwakedet
, "sys"),
197 MultiReg(rxcdrlock
, self
.rxcdrlock
, "sys"),
201 If(rxelecidle_i
!= self
.rxelecidle
,
202 If(rxelecidle_cnt_i
== 0,
203 self
.rxelecidle
.eq(rxelecidle_i
),
204 rxelecidle_cnt_i
.eq(255)
206 rxelecidle_cnt_i
.eq(rxelecidle_cnt_i
-1)
209 rxelecidle_cnt_i
.eq(255)
213 self
.rxbyteisaligned
= Signal()
216 self
.qpllclk
= Signal()
217 self
.qpllrefclk
= Signal()
220 gtxe2_channel_parameters
= {
221 # Simulation-Only Attributes
222 "p_SIM_RECEIVER_DETECT_PASS":"TRUE",
223 "p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
224 "p_SIM_RESET_SPEEDUP":"TRUE",
225 "p_SIM_CPLLREFCLK_SEL":0b001,
226 "p_SIM_VERSION":"4.0",
228 # RX Byte and Word Alignment Attributes
229 "p_ALIGN_COMMA_DOUBLE":"FALSE",
230 "p_ALIGN_COMMA_ENABLE":ones(10),
231 "p_ALIGN_COMMA_WORD":2,
232 "p_ALIGN_MCOMMA_DET":"TRUE",
233 "p_ALIGN_MCOMMA_VALUE":0b1010000011,
234 "p_ALIGN_PCOMMA_DET":"TRUE",
235 "p_ALIGN_PCOMMA_VALUE":0b0101111100,
236 "p_SHOW_REALIGN_COMMA":"FALSE",
237 "p_RXSLIDE_AUTO_WAIT":7,
238 "p_RXSLIDE_MODE":"PCS",
239 "p_RX_SIG_VALID_DLY":10,
241 # RX 8B/10B Decoder Attributes
242 "p_RX_DISPERR_SEQ_MATCH":"TRUE",
243 "p_DEC_MCOMMA_DETECT":"TRUE",
244 "p_DEC_PCOMMA_DETECT":"TRUE",
245 "p_DEC_VALID_COMMA_ONLY":"FALSE",
247 # RX Clock Correction Attributes
248 "p_CBCC_DATA_SOURCE_SEL":"DECODED",
249 "p_CLK_COR_SEQ_2_USE":"FALSE",
250 "p_CLK_COR_KEEP_IDLE":"FALSE",
251 "p_CLK_COR_MAX_LAT":9,
252 "p_CLK_COR_MIN_LAT":7,
253 "p_CLK_COR_PRECEDENCE":"TRUE",
254 "p_CLK_COR_REPEAT_WAIT":0,
255 "p_CLK_COR_SEQ_LEN":1,
256 "p_CLK_COR_SEQ_1_ENABLE":ones(4),
257 "p_CLK_COR_SEQ_1_1":0b0100000000,
258 "p_CLK_COR_SEQ_1_2":0b0000000000,
259 "p_CLK_COR_SEQ_1_3":0b0000000000,
260 "p_CLK_COR_SEQ_1_4":0b0000000000,
261 "p_CLK_CORRECT_USE":"FALSE",
262 "p_CLK_COR_SEQ_2_ENABLE":ones(4),
263 "p_CLK_COR_SEQ_2_1":0b0100000000,
264 "p_CLK_COR_SEQ_2_2":0,
265 "p_CLK_COR_SEQ_2_3":0,
266 "p_CLK_COR_SEQ_2_4":0,
268 # RX Channel Bonding Attributes
269 "p_CHAN_BOND_KEEP_ALIGN":"FALSE",
270 "p_CHAN_BOND_MAX_SKEW":1,
271 "p_CHAN_BOND_SEQ_LEN":1,
272 "p_CHAN_BOND_SEQ_1_1":0,
273 "p_CHAN_BOND_SEQ_1_1":0,
274 "p_CHAN_BOND_SEQ_1_2":0,
275 "p_CHAN_BOND_SEQ_1_3":0,
276 "p_CHAN_BOND_SEQ_1_4":0,
277 "p_CHAN_BOND_SEQ_1_ENABLE":ones(4),
278 "p_CHAN_BOND_SEQ_2_1":0,
279 "p_CHAN_BOND_SEQ_2_2":0,
280 "p_CHAN_BOND_SEQ_2_3":0,
281 "p_CHAN_BOND_SEQ_2_4":0,
282 "p_CHAN_BOND_SEQ_2_ENABLE":ones(4),
283 "p_CHAN_BOND_SEQ_2_USE":"FALSE",
284 "p_FTS_DESKEW_SEQ_ENABLE":ones(4),
285 "p_FTS_LANE_DESKEW_CFG":ones(4),
286 "p_FTS_LANE_DESKEW_EN":"FALSE",
288 # RX Margin Analysis Attributes
290 "p_ES_ERRDET_EN":"FALSE",
291 "p_ES_EYE_SCAN_EN":"TRUE",
292 "p_ES_HORZ_OFFSET":0,
298 "p_ES_VERT_OFFSET":0,
300 # FPGA RX Interface Attributes
301 "p_RX_DATA_WIDTH":20,
304 "p_OUTREFCLK_SEL_INV":0b11,
305 "p_PMA_RSV":0x00018480,
309 "p_RX_BIAS_CFG":0b100,
310 "p_DMONITOR_CFG":0xA00,
312 "p_RX_CM_TRIM":0b010,
314 "p_RX_OS_CFG":0b10000000,
316 "p_TERM_RCAL_OVRD":0,
322 # PCI Express Attributes
323 "p_PCS_PCIE_EN":"FALSE",
326 "p_PCS_RSVD_ATTR":0x100,
328 # RX Buffer Attributes
329 "p_RXBUF_ADDR_MODE":"FAST",
330 "p_RXBUF_EIDLE_HI_CNT":0b1000,
331 "p_RXBUF_EIDLE_LO_CNT":0,
334 "p_RXBUF_RESET_ON_CB_CHANGE":"TRUE",
335 "p_RXBUF_RESET_ON_COMMAALIGN":"FALSE",
336 "p_RXBUF_RESET_ON_EIDLE":"FALSE",
337 "p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE",
338 "p_RXBUFRESET_TIME":1,
339 "p_RXBUF_THRESH_OVFLW":61,
340 "p_RXBUF_THRESH_OVRD":"FALSE",
341 "p_RXBUF_THRESH_UNDFLW":4,
346 "p_RXPHDLY_CFG":0x084820,
347 "p_RXPH_MONITOR_SEL":0,
348 "p_RX_XCLK_SEL":"RXUSR",
350 "p_RX_DEFER_RESET_BUF_EN":"TRUE",
353 "p_RXCDR_CFG":rxcdr_cfg
,
354 "p_RXCDR_FR_RESET_ON_EIDLE":0,
355 "p_RXCDR_HOLD_DURING_EIDLE":0,
356 "p_RXCDR_PH_RESET_ON_EIDLE":0,
357 "p_RXCDR_LOCK_CFG":0b010101,
359 # RX Initialization and Reset Attributes
360 "p_RXCDRFREQRESET_TIME":1,
361 "p_RXCDRPHRESET_TIME":1,
362 "p_RXISCANRESET_TIME":1,
363 "p_RXPCSRESET_TIME":1,
364 "p_RXPMARESET_TIME":3,
366 # RX OOB Signaling Attributes
367 "p_RXOOB_CFG":0b0000110,
369 # RX Gearbox Attributes
370 "p_RXGEARBOX_EN":"FALSE",
373 # PRBS Detection Attribute
374 "p_RXPRBS_ERR_LOOPBACK":0,
376 # Power-Down Attributes
377 "p_PD_TRANS_TIME_FROM_P2":0x03c,
378 "p_PD_TRANS_TIME_NONE_P2":0x3c,
379 "p_PD_TRANS_TIME_TO_P2":0x64,
381 # RX OOB Signaling Attributes
384 "p_SATA_BURST_SEQ_LEN":0b0101,
385 "p_SATA_BURST_VAL":0b100,
386 "p_SATA_EIDLE_VAL":0b100,
387 "p_SATA_MAX_BURST":8,
388 "p_SATA_MAX_INIT":21,
390 "p_SATA_MIN_BURST":4,
391 "p_SATA_MIN_INIT":12,
394 # RX Fabric Clock Output Control Attributes
395 "p_TRANS_TIME_RATE":0x0e,
397 # TX Buffer Attributes
399 "p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE",
401 "p_TXDLY_LCFG":0x030,
404 "p_TXPHDLY_CFG":0x084020,
405 "p_TXPH_MONITOR_SEL":0,
406 "p_TX_XCLK_SEL":"TXOUT",
408 # FPGA TX Interface Attributes
409 "p_TX_DATA_WIDTH":20,
411 # TX Configurable Driver Attributes
414 "p_TX_EIDLE_ASSERT_DELAY":0b110,
415 "p_TX_EIDLE_DEASSERT_DELAY":0b100,
416 "p_TX_LOOPBACK_DRIVE_HIZ":"FALSE",
417 "p_TX_MAINCURSOR_SEL":0,
418 "p_TX_DRIVE_MODE":"DIRECT",
419 "p_TX_MARGIN_FULL_0":0b1001110,
420 "p_TX_MARGIN_FULL_1":0b1001001,
421 "p_TX_MARGIN_FULL_2":0b1000101,
422 "p_TX_MARGIN_FULL_3":0b1000010,
423 "p_TX_MARGIN_FULL_4":0b1000000,
424 "p_TX_MARGIN_LOW_0":0b1000110,
425 "p_TX_MARGIN_LOW_1":0b1000100,
426 "p_TX_MARGIN_LOW_2":0b1000010,
427 "p_TX_MARGIN_LOW_3":0b1000000,
428 "p_TX_MARGIN_LOW_4":0b1000000,
430 # TX Gearbox Attributes
431 "p_TXGEARBOX_EN":"FALSE",
433 # TX Initialization and Reset Attributes
434 "p_TXPCSRESET_TIME":1,
435 "p_TXPMARESET_TIME":1,
437 # TX Receiver Detection Attributes
438 "p_TX_RXDETECT_CFG":0x1832,
439 "p_TX_RXDETECT_REF":0b100,
442 "p_CPLL_CFG":0xBC07DC,
445 "p_CPLL_INIT_CFG":0x00001e,
446 "p_CPLL_LOCK_CFG":0x01e8,
447 "p_CPLL_REFCLK_DIV":1,
448 "p_RXOUT_DIV":rxout_div
,
449 "p_TXOUT_DIV":txout_div
,
450 "p_SATA_CPLL_CFG":"VCO_3000MHZ",
452 # RX Initialization and Reset Attributes
453 "p_RXDFELPMRESET_TIME":0b0001111,
455 # RX Equalizer Attributes
456 "p_RXLPM_HF_CFG":0b00000011110000,
457 "p_RXLPM_LF_CFG":0b00000011110000,
458 "p_RX_DFE_GAIN_CFG":0x020fea,
459 "p_RX_DFE_H2_CFG":0b000000000000,
460 "p_RX_DFE_H3_CFG":0b000001000000,
461 "p_RX_DFE_H4_CFG":0b00011110000,
462 "p_RX_DFE_H5_CFG":0b00011100000,
463 "p_RX_DFE_KL_CFG":0b0000011111110,
464 "p_RX_DFE_LPM_CFG":0x0954,
465 "p_RX_DFE_LPM_HOLD_DURING_EIDLE":0,
466 "p_RX_DFE_UT_CFG":0b10001111000000000,
467 "p_RX_DFE_VP_CFG":0b00011111100000011,
469 # Power-Down Attributes
473 # FPGA RX Interface Attribute
474 "p_RX_INT_DATAWIDTH":0,
476 # FPGA TX Interface Attribute
477 "p_TX_INT_DATAWIDTH":0,
479 # TX Configurable Driver Attributes
480 "p_TX_QPI_STATUS_EN":0,
482 # RX Equalizer Attributes
483 "p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100,
484 "p_RX_DFE_XYD_CFG":0b0000000000000,
486 # TX Configurable Driver Attributes
487 "p_TX_PREDRIVER_MODE":0,
491 Instance("GTXE2_CHANNEL",
494 o_CPLLLOCK
=self
.cplllock
,
499 i_CPLLREFCLKSEL
=0b001,
500 i_CPLLRESET
=self
.cpllreset
,
512 # Channel - Clocking Ports
516 i_GTREFCLK0
=self
.gtrefclk0
,
521 # Channel - DRP Ports
532 i_QPLLCLK
=self
.qpllclk
,
533 i_QPLLREFCLK
=self
.qpllrefclk
,
537 # Digital Monitor Ports
540 # FPGA TX Interface Datapath Configuration
555 # RX 8B/10B Decoder Ports
558 # RX Initialization and Reset Ports
560 i_RXUSERRDY
=rxuserrdy
,
562 # RX Margin Analysis Ports
563 #o_EYESCANDATAERROR=,
567 # Receive Ports - CDR Ports
570 o_RXCDRLOCK
=rxcdrlock
,
575 # Receive Ports - Clock Correction Ports
578 # Receive Ports - FPGA RX Interface Datapath Configuration
581 # Receive Ports - FPGA RX Interface Ports
582 i_RXUSRCLK
=self
.rxusrclk
,
583 i_RXUSRCLK2
=self
.rxusrclk2
,
585 # Receive Ports - FPGA RX interface Ports
586 o_RXDATA
=self
.rxdata
,
588 # Receive Ports - Pattern Checker Ports
592 # Receive Ports - Pattern Checker ports
595 # Receive Ports - RX Equalizer Ports
600 # Receive Ports - RX 8B/10B Decoder Ports
604 # Receive Ports - RX AFE
608 # Receive Ports - RX Buffer Bypass Ports
616 #o_RXDLYSRESETDONE=0,
627 # Receive Ports - RX Byte and Word Alignment Ports
628 o_RXBYTEISALIGNED
=self
.rxbyteisaligned
,
635 # Receive Ports - RX Channel Bonding Ports
643 # Receive Ports - RX Channel Bonding Ports
647 # Receive Ports - RX Equalizer Ports
673 # Receive Ports - RX Equilizer Ports
678 # Receive Ports - RX Fabric ClocK Output Control Ports
681 # Receive Ports - RX Fabric Output Control Ports
682 o_RXOUTCLK
=self
.rxoutclk
,
687 # Receive Ports - RX Gearbox Ports
693 # Receive Ports - RX Gearbox Ports
696 # Receive Ports - RX Initialization and Reset Ports
697 i_GTRXRESET
=self
.gtrxreset
,
700 i_RXPMARESET
=self
.pmarxreset
,
702 # Receive Ports - RX Margin Analysis ports
705 # Receive Ports - RX OOB Signaling ports
707 o_RXCOMWAKEDET
=rxcomwakedet
,
709 # Receive Ports - RX OOB Signaling ports
710 o_RXCOMINITDET
=rxcominitdet
,
712 # Receive Ports - RX OOB signalling Ports
713 o_RXELECIDLE
=rxelecidle
,
714 i_RXELECIDLEMODE
=0b00,
716 # Receive Ports - RX Polarity Control Ports
719 # Receive Ports - RX gearbox ports
722 # Receive Ports - RX8B/10B Decoder Ports
724 o_RXCHARISK
=self
.rxcharisk
,
726 # Receive Ports - Rx Channel Bonding Ports
729 # Receive Ports -RX Initialization and Reset Ports
730 o_RXRESETDONE
=rxresetdone
,
737 # TX Buffer Bypass Ports
740 # TX Configurable Driver Ports
746 i_TXQPISTRONGPDOWN
=0,
749 # TX Initialization and Reset Ports
751 i_GTTXRESET
=self
.gttxreset
,
753 i_TXUSERRDY
=txuserrdy
,
755 # Transceiver Reset Mode Operation
759 # Transmit Ports - 8b10b Encoder Control Ports
763 # Transmit Ports - FPGA TX Interface Ports
764 i_TXUSRCLK
=self
.txusrclk
,
765 i_TXUSRCLK2
=self
.txusrclk2
,
767 # Transmit Ports - PCI Express Ports
768 i_TXELECIDLE
=txelecidle
,
773 # Transmit Ports - Pattern Generator Ports
776 # Transmit Ports - TX Buffer Bypass Ports
785 #o_TXPHALIGNDONE=txphaligndone,
793 # Transmit Ports - TX Buffer Ports
796 # Transmit Ports - TX Configurable Driver Ports
797 i_TXBUFDIFFCTRL
=0b100,
805 # Transmit Ports - TX Data Path interface
806 i_TXDATA
=self
.txdata
,
808 # Transmit Ports - TX Driver and OOB signaling
812 # Transmit Ports - TX Fabric Clock Output Control Ports
813 o_TXOUTCLK
=self
.txoutclk
,
816 i_TXOUTCLKSEL
=0b11, #??
818 # Transmit Ports - TX Gearbox Ports
819 i_TXCHARISK
=self
.txcharisk
,
825 # Transmit Ports - TX Initialization and Reset Ports
828 o_TXRESETDONE
=txresetdone
,
830 # Transmit Ports - TX OOB signalling Ports
831 o_TXCOMFINISH
=txcomfinish
,
832 i_TXCOMINIT
=txcominit
,
834 i_TXCOMWAKE
=txcomwake
,
835 i_TXPDELECIDLEMODE
=0,
837 # Transmit Ports - TX Polarity Control Ports
840 # Transmit Ports - TX Receiver Detection Ports
843 # Transmit Ports - TX8b/10b Encoder Ports
846 # Transmit Ports - pattern Generator Ports
849 # Tx Configurable Driver Ports
853 **gtxe2_channel_parameters
857 class GTXE2_COMMON(Module
):
858 def __init__(self
, fbdiv
=16):
859 self
.refclk0
= Signal()
861 self
.qpllclk
= Signal()
862 self
.qpllrefclk
= Signal()
875 fbdiv_in
= fbdiv_in_config
[fbdiv
]
877 fbdiv_ratio_config
= {
887 fbdiv_ratio
= fbdiv_ratio_config
[fbdiv
]
890 Instance("GTXE2_COMMON",
891 # Simulation attributes
892 p_SIM_RESET_SPEEDUP
="TRUE",
893 p_SIM_QPLLREFCLK_SEL
=0b001,
896 # Common block attributes
897 p_BIAS_CFG
=0x0000040000001000,
899 p_QPLL_CFG
=0x06801c1,
901 p_QPLL_COARSE_FREQ_OVRD
=0b010000,
902 p_QPLL_COARSE_FREQ_OVRD_EN
=0,
903 p_QPLL_CP
=0b0000011111,
904 p_QPLL_CP_MONITOR_EN
=0,
905 p_QPLL_DMONITOR_SEL
=0,
906 p_QPLL_FBDIV
=fbdiv_in
,
907 p_QPLL_FBDIV_MONITOR_EN
=0,
908 p_QPLL_FBDIV_RATIO
=fbdiv_ratio
,
909 p_QPLL_INIT_CFG
=0x000006,
910 p_QPLL_LOCK_CFG
=0x21e9,
914 # Common block - Dynamic Reconfiguration Port (DRP)
923 # Common block - Ref Clock Ports
927 i_GTREFCLK0
=self
.refclk0
,
932 # Common block - QPLL Ports
938 o_QPLLOUTCLK
=self
.qpllclk
,
939 o_QPLLOUTREFCLK
=self
.qpllrefclk
,
943 i_QPLLREFCLKSEL
=0b001,
947 #o_REFCLKOUTMONITOR=,