liteeth/core/etherbone/wishbone.py

   1 from liteeth.common import *
   2 from migen.bus import wishbone
   3
   4 class LiteEthEtherboneWishboneMaster(Module):
   5         def __init__(self):
   6                 self.sink = sink = Sink(eth_etherbone_mmap_description(32))
   7                 self.source = source = Source(eth_etherbone_mmap_description(32))
   8                 self.bus = bus = wishbone.Interface()
   9                 ###s
  10
  11                 self.submodules.data = data = FlipFlop(32)
  12                 self.comb += data.d.eq(bus.dat_r)
  13
  14                 self.submodules.fsm = fsm = FSM(reset_state="IDLE")
  15                 fsm.act("IDLE",
  16                         sink.ack.eq(1),
  17                         If(sink.stb & sink.sop,
  18                                 sink.ack.eq(0),
  19                                 If(sink.we,
  20                                         NextState("WRITE_DATA")
  21                                 ).Else(
  22                                         NextState("READ_DATA")
  23                                 )
  24                         )
  25                 )
  26                 fsm.act("WRITE_DATA",
  27                         bus.adr.eq(sink.addr),
  28                         bus.dat_w.eq(sink.data),
  29                         bus.sel.eq(sink.be),
  30                         bus.stb.eq(sink.stb),
  31                         bus.we.eq(1),
  32                         bus.cyc.eq(1),
  33                         If(bus.stb & bus.ack,
  34                                 sink.ack.eq(1),
  35                                 If(sink.eop,
  36                                         NextState("IDLE")
  37                                 )
  38                         )
  39                 )
  40                 fsm.act("READ_DATA",
  41                         bus.adr.eq(sink.addr),
  42                         bus.sel.eq(sink.be),
  43                         bus.stb.eq(sink.stb),
  44                         bus.cyc.eq(1),
  45                         If(bus.stb & bus.ack,
  46                                 data.ce.eq(1),
  47                                 NextState("SEND_DATA")
  48                         )
  49                 )
  50                 fsm.act("SEND_DATA",
  51                         source.stb.eq(sink.stb),
  52                         source.sop.eq(sink.sop),
  53                         source.eop.eq(sink.eop),
  54                         source.base_addr.eq(sink.base_addr),
  55                         source.addr.eq(sink.addr),
  56                         source.count.eq(sink.count),
  57                         source.be.eq(sink.be),
  58                         source.we.eq(1),
  59                         source.data.eq(data.q),
  60                         If(source.stb & source.ack,
  61                                 sink.ack.eq(1),
  62                                 If(source.eop,
  63                                         NextState("IDLE")
  64                                 ).Else(
  65                                         NextState("READ_DATA")
  66                                 )
  67                         )
  68                 )