liteeth/mac/core/__init__.py

   1 from liteeth.common import *
   2 from liteeth.mac.common import *
   3 from liteeth.mac import preamble, crc, last_be
   4
   5 class LiteEthMACCore(Module, AutoCSR):
   6         def __init__(self, phy, dw, endianness="be", with_hw_preamble_crc=True):
   7                 if dw > phy.dw:
   8                         raise ValueError("Core data width must be larger than PHY data width")
   9                 # Preamble / CRC (optional)
  10                 if with_hw_preamble_crc:
  11                         self._hw_preamble_crc = CSRStatus(reset=1)
  12                         # Preamble insert/check
  13                         preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
  14                         preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
  15                         self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
  16                         self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
  17
  18                         # CRC insert/check
  19                         crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_description(phy.dw))
  20                         crc32_checker = crc.LiteEthMACCRC32Checker(eth_description(phy.dw))
  21                         self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
  22                         self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
  23
  24                 # Delimiters
  25                 tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
  26                 rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
  27                 self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
  28                 self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
  29
  30                 # Converters
  31                 reverse = endianness == "be"
  32                 tx_converter = Converter(eth_description(dw), eth_description(phy.dw), reverse=reverse)
  33                 rx_converter = Converter(eth_description(phy.dw), eth_description(dw), reverse=reverse)
  34                 self.submodules += RenameClockDomains(tx_converter, "eth_tx")
  35                 self.submodules += RenameClockDomains(rx_converter, "eth_rx")
  36
  37                 # Cross Domain Crossing
  38                 tx_cdc = AsyncFIFO(eth_description(dw), 4)
  39                 rx_cdc = AsyncFIFO(eth_description(dw), 4)
  40                 self.submodules +=  RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
  41                 self.submodules +=  RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
  42
  43                 # Graph
  44                 if with_hw_preamble_crc:
  45                         rx_pipeline = [phy, preamble_checker, crc32_checker, rx_last_be, rx_converter, rx_cdc]
  46                         tx_pipeline = [tx_cdc, tx_converter, tx_last_be, crc32_inserter, preamble_inserter, phy]
  47                 else:
  48                         rx_pipeline = [phy, rx_last_be, rx_converter, rx_cdc]
  49                         tx_pipeline = [tx_cdc, tx_converter, tx_last_be, phy]
  50                 self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
  51                 self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
  52
  53                 self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source