1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.bus
.transactions
import *
4 from migen
.sim
.generic
import run_simulation
6 from misoclib
.ethmac
import EthMAC
7 from misoclib
.ethmac
.phy
import loopback
9 from misoclib
.ethmac
.test
.common
import *
12 def __init__(self
, obj
):
16 def write(self
, adr
, dat
):
23 while self
.obj
.ack
== 0:
36 while self
.obj
.ack
== 0:
38 self
.dat
= self
.obj
.dat_r
43 class SRAMReaderDriver
:
44 def __init__(self
, obj
):
47 def start(self
, slot
, length
):
48 self
.obj
._slot
.storage
= slot
49 self
.obj
._length
.storage
= length
50 self
.obj
._start
.re
= 1
52 self
.obj
._start
.re
= 0
56 while self
.obj
.ev
.done
.pending
== 0:
60 self
.obj
.ev
.done
.clear
= 1
62 self
.obj
.ev
.done
.clear
= 0
67 self
.submodules
.ethphy
= loopback
.LoopbackPHY()
68 self
.submodules
.ethmac
= EthMAC(phy
=self
.ethphy
, with_hw_preamble_crc
=True)
70 # use sys_clk for each clock_domain
71 self
.clock_domains
.cd_eth_rx
= ClockDomain()
72 self
.clock_domains
.cd_eth_tx
= ClockDomain()
74 self
.cd_eth_rx
.clk
.eq(ClockSignal()),
75 self
.cd_eth_rx
.rst
.eq(ResetSignal()),
76 self
.cd_eth_tx
.clk
.eq(ClockSignal()),
77 self
.cd_eth_tx
.rst
.eq(ResetSignal()),
80 def gen_simulation(self
, selfp
):
81 selfp
.cd_eth_rx
.rst
= 1
82 selfp
.cd_eth_tx
.rst
= 1
84 selfp
.cd_eth_rx
.rst
= 0
85 selfp
.cd_eth_tx
.rst
= 0
87 wishbone_master
= WishboneMaster(selfp
.ethmac
.bus
)
88 sram_reader_driver
= SRAMReaderDriver(selfp
.ethmac
.sram_reader
)
90 sram_writer_slots_offset
= [0x000, 0x200]
91 sram_reader_slots_offset
= [0x400, 0x600]
95 tx_payload
= [seed_to_data(i
, True) % 0xFF for i
in range(length
)] + [0, 0, 0, 0]
100 print("slot {}:".format(slot
))
102 for i
in range(length
//4+1):
103 dat
= int.from_bytes(tx_payload
[4*i
:4*(i
+1)], "big")
104 yield from wishbone_master
.write(sram_reader_slots_offset
[slot
]+i
, dat
)
106 # send tx payload & wait
107 yield from sram_reader_driver
.start(slot
, length
)
108 yield from sram_reader_driver
.wait_done()
109 yield from sram_reader_driver
.clear_done()
111 # get rx payload (loopback on PHY Model)
113 for i
in range(length
//4+1):
114 yield from wishbone_master
.read(sram_writer_slots_offset
[slot
]+i
)
115 dat
= wishbone_master
.dat
116 rx_payload
+= list(dat
.to_bytes(4, byteorder
='big'))
119 s
, l
, e
= check(tx_payload
[:length
], rx_payload
[:min(length
, len(rx_payload
))])
120 print("shift "+ str(s
) + " / length " + str(l
) + " / errors " + str(e
))
122 if __name__
== "__main__":
123 run_simulation(TB(), vcd_name
="my.vcd")