etherbone: add etherbone_tb, able to probe etherbone endpoint
[litex.git] / liteeth / test / etherbone_tb.py
1 from migen.fhdl.std import *
2 from migen.bus import wishbone
3 from migen.bus.transactions import *
4 from migen.sim.generic import run_simulation
5
6 from liteeth.common import *
7 from liteeth.core import LiteEthUDPIPCore
8 from liteeth.core.etherbone import LiteEthEtherbone
9
10 from liteeth.test.common import *
11 from liteeth.test.model import phy, mac, arp, ip, udp, etherbone
12
13 ip_address = 0x12345678
14 mac_address = 0x12345678abcd
15
16 class TB(Module):
17 def __init__(self):
18 self.submodules.phy_model = phy.PHY(8, debug=True)
19 self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
20 self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
21 self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
22 self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=True, loopback=False)
23 self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=True)
24
25 self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
26 self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
27
28 # use sys_clk for each clock_domain
29 self.clock_domains.cd_eth_rx = ClockDomain()
30 self.clock_domains.cd_eth_tx = ClockDomain()
31 self.comb += [
32 self.cd_eth_rx.clk.eq(ClockSignal()),
33 self.cd_eth_rx.rst.eq(ResetSignal()),
34 self.cd_eth_tx.clk.eq(ClockSignal()),
35 self.cd_eth_tx.rst.eq(ResetSignal()),
36 ]
37
38 def gen_simulation(self, selfp):
39 selfp.cd_eth_rx.rst = 1
40 selfp.cd_eth_tx.rst = 1
41 yield
42 selfp.cd_eth_rx.rst = 0
43 selfp.cd_eth_tx.rst = 0
44
45 for i in range(100):
46 yield
47
48 # test probe
49 packet = etherbone.EtherbonePacket()
50 packet.pf = 1
51 self.etherbone_model.send(packet)
52
53 if __name__ == "__main__":
54 run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)