1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.bus
.transactions
import *
4 from migen
.sim
.generic
import run_simulation
6 from liteeth
.common
import *
7 from liteeth
.core
import LiteEthIPCore
9 from liteeth
.test
.common
import *
10 from liteeth
.test
.model
.dumps
import *
11 from liteeth
.test
.model
.mac
import *
12 from liteeth
.test
.model
.ip
import *
13 from liteeth
.test
.model
.icmp
import *
14 from liteeth
.test
.model
import phy
, mac
, arp
, ip
, icmp
16 ip_address
= 0x12345678
17 mac_address
= 0x12345678abcd
21 self
.submodules
.phy_model
= phy
.PHY(8, debug
=True)
22 self
.submodules
.mac_model
= mac
.MAC(self
.phy_model
, debug
=True, loopback
=False)
23 self
.submodules
.arp_model
= arp
.ARP(self
.mac_model
, mac_address
, ip_address
, debug
=True)
24 self
.submodules
.ip_model
= ip
.IP(self
.mac_model
, mac_address
, ip_address
, debug
=True, loopback
=False)
25 self
.submodules
.icmp_model
= icmp
.ICMP(self
.ip_model
, ip_address
, debug
=True)
27 self
.submodules
.ip
= LiteEthIPCore(self
.phy_model
, mac_address
, ip_address
, 100000)
29 # use sys_clk for each clock_domain
30 self
.clock_domains
.cd_eth_rx
= ClockDomain()
31 self
.clock_domains
.cd_eth_tx
= ClockDomain()
33 self
.cd_eth_rx
.clk
.eq(ClockSignal()),
34 self
.cd_eth_rx
.rst
.eq(ResetSignal()),
35 self
.cd_eth_tx
.clk
.eq(ClockSignal()),
36 self
.cd_eth_tx
.rst
.eq(ResetSignal()),
39 def gen_simulation(self
, selfp
):
40 selfp
.cd_eth_rx
.rst
= 1
41 selfp
.cd_eth_tx
.rst
= 1
43 selfp
.cd_eth_rx
.rst
= 0
44 selfp
.cd_eth_tx
.rst
= 0
49 packet
= MACPacket(ping_request
)
50 packet
.decode_remove_header()
51 packet
= IPPacket(packet
)
53 packet
= ICMPPacket(packet
)
55 self
.icmp_model
.send(packet
)
57 if __name__
== "__main__":
58 run_simulation(TB(), ncycles
=2048, vcd_name
="my.vcd", keep_files
=True)