liteeth/test/mac_wishbone_tb.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3 from migen.bus.transactions import *
   4 from migen.sim.generic import run_simulation
   5
   6 from misoclib.ethmac import EthMAC
   7 from misoclib.ethmac.phy import loopback
   8
   9 from misoclib.ethmac.test.common import *
  10
  11 class WishboneMaster:
  12         def __init__(self, obj):
  13                 self.obj = obj
  14                 self.dat = 0
  15
  16         def write(self, adr, dat):
  17                 self.obj.cyc = 1
  18                 self.obj.stb = 1
  19                 self.obj.adr = adr
  20                 self.obj.we = 1
  21                 self.obj.sel = 0xF
  22                 self.obj.dat_w = dat
  23                 while self.obj.ack == 0:
  24                         yield
  25                 self.obj.cyc = 0
  26                 self.obj.stb = 0
  27                 yield
  28
  29         def read(self, adr):
  30                 self.obj.cyc = 1
  31                 self.obj.stb = 1
  32                 self.obj.adr = adr
  33                 self.obj.we = 0
  34                 self.obj.sel = 0xF
  35                 self.obj.dat_w = 0
  36                 while self.obj.ack == 0:
  37                         yield
  38                 self.dat = self.obj.dat_r
  39                 self.obj.cyc = 0
  40                 self.obj.stb = 0
  41                 yield
  42
  43 class SRAMReaderDriver:
  44         def __init__(self, obj):
  45                 self.obj = obj
  46
  47         def start(self, slot, length):
  48                 self.obj._slot.storage = slot
  49                 self.obj._length.storage = length
  50                 self.obj._start.re = 1
  51                 yield
  52                 self.obj._start.re = 0
  53                 yield
  54
  55         def wait_done(self):
  56                 while self.obj.ev.done.pending == 0:
  57                         yield
  58
  59         def clear_done(self):
  60                 self.obj.ev.done.clear = 1
  61                 yield
  62                 self.obj.ev.done.clear = 0
  63                 yield
  64
  65 class TB(Module):
  66         def __init__(self):
  67                 self.submodules.ethphy = loopback.LoopbackPHY()
  68                 self.submodules.ethmac = EthMAC(phy=self.ethphy, with_hw_preamble_crc=True)
  69
  70                 # use sys_clk for each clock_domain
  71                 self.clock_domains.cd_eth_rx = ClockDomain()
  72                 self.clock_domains.cd_eth_tx = ClockDomain()
  73                 self.comb += [
  74                         self.cd_eth_rx.clk.eq(ClockSignal()),
  75                         self.cd_eth_rx.rst.eq(ResetSignal()),
  76                         self.cd_eth_tx.clk.eq(ClockSignal()),
  77                         self.cd_eth_tx.rst.eq(ResetSignal()),
  78                 ]
  79
  80         def gen_simulation(self, selfp):
  81                 selfp.cd_eth_rx.rst = 1
  82                 selfp.cd_eth_tx.rst = 1
  83                 yield
  84                 selfp.cd_eth_rx.rst = 0
  85                 selfp.cd_eth_tx.rst = 0
  86
  87                 wishbone_master = WishboneMaster(selfp.ethmac.bus)
  88                 sram_reader_driver = SRAMReaderDriver(selfp.ethmac.sram_reader)
  89
  90                 sram_writer_slots_offset = [0x000, 0x200]
  91                 sram_reader_slots_offset = [0x400, 0x600]
  92
  93                 length = 1500+2
  94
  95                 tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0]
  96
  97                 errors = 0
  98
  99                 for slot in range(2):
 100                         print("slot {}:".format(slot))
 101                         # fill tx memory
 102                         for i in range(length//4+1):
 103                                 dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
 104                                 yield from wishbone_master.write(sram_reader_slots_offset[slot]+i, dat)
 105
 106                         # send tx payload & wait
 107                         yield from sram_reader_driver.start(slot, length)
 108                         yield from sram_reader_driver.wait_done()
 109                         yield from sram_reader_driver.clear_done()
 110
 111                         # get rx payload (loopback on PHY Model)
 112                         rx_payload = []
 113                         for i in range(length//4+1):
 114                                 yield from wishbone_master.read(sram_writer_slots_offset[slot]+i)
 115                                 dat = wishbone_master.dat
 116                                 rx_payload += list(dat.to_bytes(4, byteorder='big'))
 117
 118                         # check results
 119                         s, l, e = check(tx_payload[:length], rx_payload[:min(length, len(rx_payload))])
 120                         print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
 121
 122 if __name__ == "__main__":
 123         run_simulation(TB(), vcd_name="my.vcd")