change submodules/specials/clock_domains syntax
[litex.git] / litesata / __init__.py
1 from litesata.common import *
2 from litesata.phy import *
3 from litesata.core import *
4 from litesata.frontend import *
5
6 from migen.bank.description import *
7
8 class LiteSATA(Module, AutoCSR):
9 def __init__(self, phy, buffer_depth=2*fis_max_dwords,
10 with_bist=False, with_bist_csr=False):
11 # phy
12 self.phy = phy
13
14 # core
15 self.submodules.core = LiteSATACore(self.phy, buffer_depth)
16
17 # frontend
18 self.submodules.crossbar = LiteSATACrossbar(self.core)
19 if with_bist:
20 self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
21