1 from litesata
.common
import *
2 from litesata
.core
.link
.scrambler
import Scrambler
4 class LiteSATACONTInserter(Module
):
5 def __init__(self
, description
):
6 self
.sink
= sink
= Sink(description
)
7 self
.source
= source
= Source(description
)
11 counter
= Counter(max=4)
12 self
.submodules
+= counter
18 self
.comb
+= is_data
.eq(sink
.charisk
== 0)
20 last_data
= Signal(32)
21 last_primitive
= Signal(32)
22 last_charisk
= Signal(4)
24 If(sink
.stb
& source
.ack
,
25 last_data
.eq(sink
.data
),
26 last_charisk
.eq(sink
.charisk
),
28 last_primitive
.eq(sink
.data
),
31 was_hold
.eq(last_primitive
== primitives
["HOLD"])
34 self
.comb
+= change
.eq(
35 (sink
.data
!= last_data
) |
36 (sink
.charisk
!= last_charisk
) |
41 scrambler
= InsertReset(Scrambler())
42 self
.submodules
+= scrambler
46 Record
.connect(sink
, source
),
49 counter
.ce
.eq(sink
.ack
& (counter
.value
!=2)),
51 If(counter
.value
== 1,
52 source
.charisk
.eq(0b0001),
53 source
.data
.eq(primitives
["CONT"])
54 # insert scrambled data for EMI
55 ).Elif(counter
.value
== 2,
56 scrambler
.ce
.eq(sink
.ack
),
57 source
.charisk
.eq(0b0000),
58 source
.data
.eq(scrambler
.value
)
61 counter
.reset
.eq(source
.ack
),
62 If(counter
.value
== 2,
63 # Reinsert last primitive
64 If(is_data |
(~is_data
& was_hold
),
67 source
.charisk
.eq(0b0001),
68 source
.data
.eq(last_primitive
)
75 class LiteSATACONTRemover(Module
):
76 def __init__(self
, description
):
77 self
.sink
= sink
= Sink(description
)
78 self
.source
= source
= Source(description
)
85 cont_ongoing
= Signal()
88 is_data
.eq(sink
.charisk
== 0),
89 is_cont
.eq(~is_data
& (sink
.data
== primitives
["CONT"]))
92 If(sink
.stb
& sink
.ack
,
99 self
.comb
+= cont_ongoing
.eq(is_cont |
(in_cont
& is_data
))
102 last_primitive
= Signal(32)
104 If(sink
.stb
& sink
.ack
,
105 If(~is_data
& ~is_cont
,
106 last_primitive
.eq(sink
.data
)
111 Record
.connect(sink
, source
),
113 source
.charisk
.eq(0b0001),
114 source
.data
.eq(last_primitive
)