change submodules/specials/clock_domains syntax
[litex.git] / litesata / frontend / arbiter.py
1 from litesata.common import *
2 from litesata.frontend.common import *
3
4 from migen.genlib.roundrobin import *
5
6 class LiteSATAArbiter(Module):
7 def __init__(self, users, master):
8 self.rr = RoundRobin(len(users))
9 self.submodules += self.rr
10 self.grant = self.rr.grant
11 cases = {}
12 for i, slave in enumerate(users):
13 sink, source = slave.sink, slave.source
14 start = Signal()
15 done = Signal()
16 ongoing = Signal()
17 self.comb += [
18 start.eq(sink.stb & sink.sop),
19 done.eq(source.stb & source.last & source.eop & source.ack)
20 ]
21 self.sync += \
22 If(start,
23 ongoing.eq(1)
24 ).Elif(done,
25 ongoing.eq(0)
26 )
27 self.comb += self.rr.request[i].eq((start | ongoing) & ~done)
28 cases[i] = [users[i].connect(master)]
29 self.comb += Case(self.grant, cases)