litex/boards/platforms/ac701.py

   1 # This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
   2 # License: BSD
   3
   4 from litex.build.generic_platform import *
   5 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   6
   7 # IOs ----------------------------------------------------------------------------------------------
   8
   9 _io = [
  10     ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
  11     ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
  12     ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
  13     ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
  14
  15     ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
  16
  17     ("clk200", 0,
  18         Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
  19         Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
  20     ),
  21
  22     ("clk156", 0,
  23         Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
  24         Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
  25     ),
  26
  27     ("serial", 0,
  28         Subsignal("cts", Pins("V19")),
  29         Subsignal("rts", Pins("W19")),
  30         Subsignal("tx", Pins("U19")),
  31         Subsignal("rx", Pins("T19")),
  32         IOStandard("LVCMOS18")
  33     ),
  34
  35     ("eth_clocks", 0,
  36         Subsignal("tx", Pins("U22")),
  37         Subsignal("rx", Pins("U21")),
  38         IOStandard("LVCMOS18")
  39     ),
  40
  41     ("eth", 0,
  42      Subsignal("rx_ctl", Pins("U14")),
  43      Subsignal("rx_data", Pins("U17 V17 V16 V14")),
  44      Subsignal("tx_ctl", Pins("T15")),
  45      Subsignal("tx_data", Pins("U16 U15 T18 T17")),
  46      Subsignal("rst_n", Pins("V18")),
  47      Subsignal("mdc", Pins("W18")),
  48      Subsignal("mdio", Pins("T14")),
  49      IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
  50     ),
  51
  52
  53     ("ddram", 0,
  54         Subsignal("a", Pins(
  55             "M4 J3 J1 L4 K5 M7 K1 M6",
  56             "H1 K3 N7 L5 L7 N6 L3 K2"),
  57             IOStandard("SSTL15")),
  58         Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
  59         Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
  60         Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
  61         Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
  62         Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
  63         Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
  64             IOStandard("SSTL15")),
  65         Subsignal("dq", Pins(
  66           "AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
  67           "AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
  68           "AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
  69           "Y3 W3 W6 V6 W4 W5 W1 V1",
  70           "G2 D1 E1 E2 F2 A2 A3 C2",
  71           "C3 D3 A4 B4 C4 D4 D5 E5",
  72           "F4 G4 K6 K7 K8 L8 J5 J6",
  73           "G6 H6 F7 F8 G8 H8 D6 E6"),
  74                   IOStandard("SSTL15")),
  75         Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
  76             IOStandard("DIFF_SSTL15")),
  77         Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
  78             IOStandard("DIFF_SSTL15")),
  79         Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
  80         Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
  81         Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
  82         Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
  83         Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
  84     ),
  85
  86     ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
  87
  88     ("gtp_refclk", 0,
  89      Subsignal("p", Pins("AA13")),
  90      Subsignal("n", Pins("AB13"))
  91     ),
  92
  93     ("sfp", 0,
  94         Subsignal("txp", Pins("AC10")),
  95         Subsignal("txn", Pins("AD10")),
  96         Subsignal("rxp", Pins("AC12")),
  97         Subsignal("rxn", Pins("AD12")),
  98     ),
  99     ("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
 100     ("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
 101     ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
 102     ("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
 103 ]
 104
 105 # Connectors ---------------------------------------------------------------------------------------
 106
 107 _connectors = [
 108     ("HPC", {
 109       "CLK0_M2C_N": "C19",
 110       "CLK0_M2C_P": "D19",
 111       "CLK1_M2C_N": "H22",
 112       "CLK1_M2C_P": "H21",
 113       "LA00_CC_N": "C18",
 114       "LA00_CC_P": "D18",
 115       "LA01_CC_N": "E18",
 116       "LA01_CC_P": "E17",
 117       "LA02_N": "H15",
 118       "LA02_P": "H14",
 119       "LA03_N": "F17",
 120       "LA03_P": "G17",
 121       "LA04_N": "F19",
 122       "LA04_P": "F18",
 123       "LA05_N": "F15",
 124       "LA05_P": "G15",
 125       "LA06_N": "F20",
 126       "LA06_P": "G19",
 127       "LA07_N": "G16",
 128       "LA07_P": "H16",
 129       "LA08_N": "B17",
 130       "LA08_P": "C17",
 131       "LA09_N": "D16",
 132       "LA09_P": "E16",
 133       "LA10_N": "A18",
 134       "LA10_P": "A17",
 135       "LA11_N": "A19",
 136       "LA11_P": "B19",
 137       "LA12_N": "D20",
 138       "LA12_P": "E20",
 139       "LA13_N": "A20",
 140       "LA13_P": "B20",
 141       "LA14_N": "B21",
 142       "LA14_P": "C21",
 143       "LA15_N": "A22",
 144       "LA15_P": "B22",
 145       "LA16_N": "D21",
 146       "LA16_P": "E21",
 147       "LA17_CC_N": "J21",
 148       "LA17_CC_P": "K21",
 149       "LA18_CC_N": "G21",
 150       "LA18_CC_P": "G20",
 151       "LA19_N": "L14",
 152       "LA19_P": "M14",
 153       "LA20_N": "M17",
 154       "LA20_P": "M16",
 155       "LA21_N": "H19",
 156       "LA21_P": "J19",
 157       "LA22_N": "L18",
 158       "LA22_P": "L17",
 159       "LA23_N": "J20",
 160       "LA23_P": "K20",
 161       "LA24_N": "H18",
 162       "LA24_P": "J18",
 163       "LA25_N": "F22",
 164       "LA25_P": "G22",
 165       "LA26_N": "H24",
 166       "LA26_P": "J24",
 167       "LA27_N": "E23",
 168       "LA27_P": "F23",
 169       "LA28_N": "K23",
 170       "LA28_P": "K22",
 171       "LA29_N": "F24",
 172       "LA29_P": "G24",
 173       "LA30_N": "D25",
 174       "LA30_P": "E25",
 175       "LA31_N": "D26",
 176       "LA31_P": "E26",
 177       "LA32_N": "G26",
 178       "LA32_P": "H26",
 179       "LA33_N": "F25",
 180       "LA33_P": "G25",
 181       "PRSNT_M2C_L": "N16",
 182       "PWR_GOOD_FLASH_RST_B": "P15"}
 183     ),
 184     ("XADC", {
 185         "GPIO0": "H17",
 186         "GPIO1": "E22",
 187         "GPIO2": "K18",
 188         "GPIO3": "L19",
 189         "VAUX0_N": "J16",
 190         "VAUX0_P": "K15",
 191         "VAUX8_N": "J15",
 192         "VAUX8_P": "J14",
 193         }
 194     ),
 195 ]
 196
 197 # Platform -----------------------------------------------------------------------------------------
 198
 199 class Platform(XilinxPlatform):
 200     default_clk_name = "clk156"
 201     default_clk_period = 6.4
 202
 203     def __init__(self):
 204         XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
 205         self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 206         self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 207
 208     def create_programmer(self):
 209         return VivadoProgrammer()
 210
 211     def do_finalize(self, fragment):
 212         XilinxPlatform.do_finalize(self, fragment)
 213         try:
 214             self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
 215         except ConstraintError:
 216             pass
 217         try:
 218             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
 219         except ConstraintError:
 220             pass
 221         try:
 222             self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
 223         except ConstraintError:
 224             pass