1 # This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
4 from litex
.build
.generic_platform
import *
5 from litex
.build
.xilinx
import XilinxPlatform
, VivadoProgrammer
7 # IOs ----------------------------------------------------------------------------------------------
10 ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
11 ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
12 ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
13 ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
15 ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
18 Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
19 Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
23 Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
24 Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
28 Subsignal("cts", Pins("V19")),
29 Subsignal("rts", Pins("W19")),
30 Subsignal("tx", Pins("U19")),
31 Subsignal("rx", Pins("T19")),
32 IOStandard("LVCMOS18")
36 Subsignal("tx", Pins("U22")),
37 Subsignal("rx", Pins("U21")),
38 IOStandard("LVCMOS18")
42 Subsignal("rx_ctl", Pins("U14")),
43 Subsignal("rx_data", Pins("U17 V17 V16 V14")),
44 Subsignal("tx_ctl", Pins("T15")),
45 Subsignal("tx_data", Pins("U16 U15 T18 T17")),
46 Subsignal("rst_n", Pins("V18")),
47 Subsignal("mdc", Pins("W18")),
48 Subsignal("mdio", Pins("T14")),
49 IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
55 "M4 J3 J1 L4 K5 M7 K1 M6",
56 "H1 K3 N7 L5 L7 N6 L3 K2"),
57 IOStandard("SSTL15")),
58 Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
59 Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
60 Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
61 Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
62 Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
63 Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
64 IOStandard("SSTL15")),
66 "AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
67 "AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
68 "AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
69 "Y3 W3 W6 V6 W4 W5 W1 V1",
70 "G2 D1 E1 E2 F2 A2 A3 C2",
71 "C3 D3 A4 B4 C4 D4 D5 E5",
72 "F4 G4 K6 K7 K8 L8 J5 J6",
73 "G6 H6 F7 F8 G8 H8 D6 E6"),
74 IOStandard("SSTL15")),
75 Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
76 IOStandard("DIFF_SSTL15")),
77 Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
78 IOStandard("DIFF_SSTL15")),
79 Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
80 Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
81 Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
82 Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
83 Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
86 ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
89 Subsignal("p", Pins("AA13")),
90 Subsignal("n", Pins("AB13"))
94 Subsignal("txp", Pins("AC10")),
95 Subsignal("txn", Pins("AD10")),
96 Subsignal("rxp", Pins("AC12")),
97 Subsignal("rxn", Pins("AD12")),
99 ("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
100 ("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
101 ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
102 ("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
105 # Connectors ---------------------------------------------------------------------------------------
181 "PRSNT_M2C_L": "N16",
182 "PWR_GOOD_FLASH_RST_B": "P15"}
197 # Platform -----------------------------------------------------------------------------------------
199 class Platform(XilinxPlatform
):
200 default_clk_name
= "clk156"
201 default_clk_period
= 6.4
204 XilinxPlatform
.__init
__(self
, "xc7a200t-fbg676-2", _io
, _connectors
, toolchain
="vivado")
205 self
.toolchain
.bitstream_commands
= ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
206 self
.toolchain
.additional_commands
= ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
208 def create_programmer(self
):
209 return VivadoProgrammer()
211 def do_finalize(self
, fragment
):
212 XilinxPlatform
.do_finalize(self
, fragment
)
214 self
.add_period_constraint(self
.lookup_request("clk200").p
, 1e9
/200e6
)
215 except ConstraintError
:
218 self
.add_period_constraint(self
.lookup_request("eth_clocks").rx
, 1e9
/125e6
)
219 except ConstraintError
:
222 self
.add_period_constraint(self
.lookup_request("eth_clocks").tx
, 1e9
/125e6
)
223 except ConstraintError
: