litex/boards/platforms/arty.py

   1 # This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
   2 # This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
   3 # This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
   4 # This file is Copyright (c) 2018 Caleb Jamison <cbjamo@gmail.com>
   5 # License: BSD
   6
   7 from litex.build.generic_platform import *
   8 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   9
  10 # IOs ----------------------------------------------------------------------------------------------
  11
  12 _io = [
  13     ("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
  14     ("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
  15     ("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
  16     ("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
  17
  18     ("rgb_led", 0,
  19         Subsignal("r", Pins("G6")),
  20         Subsignal("g", Pins("F6")),
  21         Subsignal("b", Pins("E1")),
  22         IOStandard("LVCMOS33"),
  23     ),
  24
  25     ("rgb_led", 1,
  26         Subsignal("r", Pins("G3")),
  27         Subsignal("g", Pins("J4")),
  28         Subsignal("b", Pins("G4")),
  29         IOStandard("LVCMOS33"),
  30     ),
  31
  32     ("rgb_led", 2,
  33         Subsignal("r", Pins("J3")),
  34         Subsignal("g", Pins("J2")),
  35         Subsignal("b", Pins("H4")),
  36         IOStandard("LVCMOS33"),
  37     ),
  38
  39     ("rgb_led", 3,
  40         Subsignal("r", Pins("K1")),
  41         Subsignal("g", Pins("H6")),
  42         Subsignal("b", Pins("K2")),
  43         IOStandard("LVCMOS33"),
  44     ),
  45
  46     ("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
  47     ("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
  48     ("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
  49     ("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
  50
  51     ("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
  52     ("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
  53     ("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
  54     ("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
  55
  56     ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
  57
  58     ("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
  59
  60     ("serial", 0,
  61         Subsignal("tx", Pins("D10")),
  62         Subsignal("rx", Pins("A9")),
  63         IOStandard("LVCMOS33")
  64     ),
  65
  66     ("spi", 0,
  67         Subsignal("clk", Pins("F1")),
  68         Subsignal("cs_n", Pins("C1")),
  69         Subsignal("mosi", Pins("H1")),
  70         Subsignal("miso", Pins("G1")),
  71         IOStandard("LVCMOS33"),
  72     ),
  73
  74     ("i2c", 0,
  75         Subsignal("scl", Pins("L18")),
  76         Subsignal("sda", Pins("M18")),
  77         Subsignal("scl_pup", Pins("A14")),
  78         Subsignal("sda_pup", Pins("A13")),
  79         IOStandard("LVCMOS33"),
  80     ),
  81
  82     ("spiflash4x", 0,  # clock needs to be accessed through STARTUPE2
  83         Subsignal("cs_n", Pins("L13")),
  84         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
  85         IOStandard("LVCMOS33")
  86     ),
  87     ("spiflash", 0,  # clock needs to be accessed through STARTUPE2
  88         Subsignal("cs_n", Pins("L13")),
  89         Subsignal("mosi", Pins("K17")),
  90         Subsignal("miso", Pins("K18")),
  91         Subsignal("wp", Pins("L14")),
  92         Subsignal("hold", Pins("M14")),
  93         IOStandard("LVCMOS33"),
  94     ),
  95
  96     ("ddram", 0,
  97         Subsignal("a", Pins(
  98             "R2 M6 N4 T1 N6 R7 V6 U7",
  99             "R8 V7 R6 U6 T6 T8"),
 100             IOStandard("SSTL135")),
 101         Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
 102         Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
 103         Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
 104         Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
 105         Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
 106         Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")),
 107         Subsignal("dq", Pins(
 108             "K5 L3 K3 L6 M3 M1 L4 M2",
 109             "V4 T5 U4 V5 V1 T3 U3 R3"),
 110             IOStandard("SSTL135"),
 111             Misc("IN_TERM=UNTUNED_SPLIT_40")),
 112         Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")),
 113         Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")),
 114         Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
 115         Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
 116         Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
 117         Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
 118         Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
 119         Misc("SLEW=FAST"),
 120     ),
 121
 122     ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
 123     ("eth_clocks", 0,
 124         Subsignal("tx", Pins("H16")),
 125         Subsignal("rx", Pins("F15")),
 126         IOStandard("LVCMOS33"),
 127     ),
 128     ("eth", 0,
 129         Subsignal("rst_n", Pins("C16")),
 130         Subsignal("mdio", Pins("K13")),
 131         Subsignal("mdc", Pins("F16")),
 132         Subsignal("rx_dv", Pins("G16")),
 133         Subsignal("rx_er", Pins("C17")),
 134         Subsignal("rx_data", Pins("D18 E17 E18 G17")),
 135         Subsignal("tx_en", Pins("H15")),
 136         Subsignal("tx_data", Pins("H14 J14 J13 H17")),
 137         Subsignal("col", Pins("D17")),
 138         Subsignal("crs", Pins("G14")),
 139         IOStandard("LVCMOS33"),
 140     ),
 141 ]
 142
 143 # Connectors ---------------------------------------------------------------------------------------
 144
 145 _connectors = [
 146     ("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
 147     ("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
 148     ("pmodc", "U12 V12 V10 V11 U14 V14 T13 U13"),
 149     ("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"),
 150     ("ck_io", {
 151         # Outer Digital Header
 152         "ck_io0" : "V15",
 153         "ck_io1" : "U16",
 154         "ck_io2" : "P14",
 155         "ck_io3" : "T11",
 156         "ck_io4" : "R12",
 157         "ck_io5" : "T14",
 158         "ck_io6" : "T15",
 159         "ck_io7" : "T16",
 160         "ck_io8" : "N15",
 161         "ck_io9" : "M16",
 162         "ck_io10" : "V17",
 163         "ck_io11" : "U18",
 164         "ck_io12" : "R17",
 165         "ck_io13" : "P17",
 166
 167         # Inner Digital Header
 168         "ck_io26" : "U11",
 169         "ck_io27" : "V16",
 170         "ck_io28" : "M13",
 171         "ck_io29" : "R10",
 172         "ck_io30" : "R11",
 173         "ck_io31" : "R13",
 174         "ck_io32" : "R15",
 175         "ck_io33" : "P15",
 176         "ck_io34" : "R16",
 177         "ck_io35" : "N16",
 178         "ck_io36" : "N14",
 179         "ck_io37" : "U17",
 180         "ck_io38" : "T18",
 181         "ck_io39" : "R18",
 182         "ck_io40" : "P18",
 183         "ck_io41" : "N17",
 184
 185         # Outer Analog Header as Digital IO
 186         "ck_a0" : "F5",
 187         "ck_a1" : "D8",
 188         "ck_a2" : "C7",
 189         "ck_a3" : "E7",
 190         "ck_a4" : "D7",
 191         "ck_a5" : "D5",
 192
 193         # Inner Analog Header as Digital IO
 194         "ck_io20" : "B7",
 195         "ck_io21" : "B6",
 196         "ck_io22" : "E6",
 197         "ck_io23" : "E5",
 198         "ck_io24" : "A4",
 199         "ck_io25" : "A3",
 200         } ),
 201     ("XADC", {
 202         # Outer Analog Header
 203         "vaux4_n" : "C5",
 204         "vaux4_p" : "C6",
 205         "vaux5_n" : "A5",
 206         "vaux5_p" : "A6",
 207         "vaux6_n" : "B4",
 208         "vaux6_p" : "C4",
 209         "vaux7_n" : "A1",
 210         "vaux7_p" : "B1",
 211         "vaux15_n" : "B2",
 212         "vaux15_p" : "B3",
 213         "vaux0_n" : "C14",
 214         "vaux0_p" : "D14",
 215
 216         # Inner Analog Header
 217         "vaux12_n" : "B7",
 218         "vaux12_p" : "B6",
 219         "vaux13_n" : "E6",
 220         "vaux13_p" : "E5",
 221         "vaux14_n" : "A4",
 222         "vaux14_p" : "A3",
 223
 224         # Power Measurements
 225         "vsnsuv_n" : "B17",
 226         "vsnsuv_p" : "B16",
 227         "vsns5v0_n" : "B12",
 228         "vsns5v0_p" : "C12",
 229         "isns5v0_n" : "F14",
 230         "isns5v0_n" : "F13",
 231         "isns0v95_n" : "A16",
 232         "isns0v95_n" : "A15",
 233         } ),
 234 ]
 235
 236 # Platform -----------------------------------------------------------------------------------------
 237
 238 class Platform(XilinxPlatform):
 239     default_clk_name = "clk100"
 240     default_clk_period = 10.0
 241
 242     def __init__(self):
 243         XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain="vivado")
 244         self.toolchain.bitstream_commands = \
 245             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
 246         self.toolchain.additional_commands = \
 247             ["write_cfgmem -force -format bin -interface spix4 -size 16 "
 248              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 249         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
 250
 251     def create_programmer(self):
 252         return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")