litex/boards/platforms/kcu105.py

   1 from litex.build.generic_platform import *
   2 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   3
   4
   5 _io = [
   6     ("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
   7     ("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
   8     ("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
   9     ("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
  10     ("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
  11     ("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
  12     ("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
  13     ("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
  14
  15     ("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
  16
  17     ("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
  18     ("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
  19     ("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
  20     ("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
  21     ("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
  22
  23     ("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
  24     ("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
  25     ("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
  26     ("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
  27
  28     ("user_sma_clock", 0,
  29         Subsignal("p", Pins("D23"), IOStandard("LVDS")),
  30         Subsignal("n", Pins("C23"), IOStandard("LVDS"))
  31     ),
  32     ("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
  33     ("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
  34
  35     ("user_sma_gpio", 0,
  36         Subsignal("p", Pins("H27"), IOStandard("LVDS")),
  37         Subsignal("n", Pins("G27"), IOStandard("LVDS"))
  38     ),
  39     ("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")),
  40     ("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")),
  41
  42     ("clk125", 0,
  43         Subsignal("p", Pins("G10"), IOStandard("LVDS")),
  44         Subsignal("n", Pins("F10"), IOStandard("LVDS"))
  45     ),
  46
  47     ("clk300", 0,
  48         Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
  49         Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
  50     ),
  51
  52     ("i2c", 0,
  53         Subsignal("scl", Pins("J24")),
  54         Subsignal("sda", Pins("J25")),
  55         IOStandard("LVCMOS18")
  56     ),
  57
  58     ("serial", 0,
  59         Subsignal("cts", Pins("L23")),
  60         Subsignal("rts", Pins("K27")),
  61         Subsignal("tx", Pins("K26")),
  62         Subsignal("rx", Pins("G25")),
  63         IOStandard("LVCMOS18")
  64     ),
  65
  66     ("spiflash", 0,  # clock needs to be accessed through primitive
  67         Subsignal("cs_n", Pins("U7")),
  68         Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
  69         IOStandard("LVCMOS18")
  70     ),
  71
  72     ("spiflash", 1,  # clock needs to be accessed through primitive
  73         Subsignal("cs_n", Pins("G26")),
  74         Subsignal("dq", Pins("M20 L20 R21 R22")),
  75         IOStandard("LVCMOS18")
  76     ),
  77
  78     ("rotary", 0,
  79         Subsignal("a", Pins("Y21")),
  80         Subsignal("b", Pins("AD26")),
  81         Subsignal("push", Pins("AF28")),
  82         IOStandard("LVCMOS18")
  83     ),
  84
  85     ("hdmi", 0,
  86         Subsignal("d", Pins(
  87             "AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
  88             "AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
  89             "AG10 AK8")),
  90         Subsignal("de", Pins("AE11")),
  91         Subsignal("clk", Pins("AF13")),
  92         Subsignal("vsync", Pins("AH13")),
  93         Subsignal("hsync", Pins("AE13")),
  94         Subsignal("spdif", Pins("AE12")),
  95         Subsignal("spdif_out", Pins("AF12")),
  96         IOStandard("LVCMOS18")
  97     ),
  98
  99     ("ddram", 0,
 100         Subsignal("a", Pins(
 101             "AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
 102             "AF18 AH19 AF15 AD19 AJ14 AG19"),
 103             IOStandard("SSTL12_DCI")),
 104         Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
 105         Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
 106         Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")),  # A16
 107         Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")),  # A15
 108         Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")),   # A14
 109         Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
 110         Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
 111         Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
 112         Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
 113         Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
 114         Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
 115             IOStandard("POD12_DCI")),
 116         Subsignal("dq", Pins(
 117             "AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
 118             "AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
 119
 120             "AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
 121             "AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
 122
 123             "AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
 124             "AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
 125
 126             "AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
 127             "AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32",
 128             ),
 129             IOStandard("POD12_DCI")),
 130         Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
 131             IOStandard("DIFF_POD12")),
 132         Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
 133             IOStandard("DIFF_POD12")),
 134         Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
 135         Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
 136         Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
 137         Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
 138         Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
 139         Misc("SLEW=FAST"),
 140     ),
 141
 142     ("pcie_x1", 0,
 143         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 144         Subsignal("clk_p", Pins("AB6")),
 145         Subsignal("clk_n", Pins("AB5")),
 146         Subsignal("rx_p", Pins("AB2")),
 147         Subsignal("rx_n", Pins("AB1")),
 148         Subsignal("tx_p", Pins("AC3")),
 149         Subsignal("tx_n", Pins("AC4"))
 150     ),
 151
 152     ("pcie_x2", 0,
 153         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 154         Subsignal("clk_p", Pins("AB6")),
 155         Subsignal("clk_n", Pins("AB5")),
 156         Subsignal("rx_p", Pins("AB2 AD2")),
 157         Subsignal("rx_n", Pins("AB1 AD1")),
 158         Subsignal("tx_p", Pins("AC3 AE4")),
 159         Subsignal("tx_n", Pins("AC4 AE3"))
 160     ),
 161
 162     ("pcie_x4", 0,
 163         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 164         Subsignal("clk_p", Pins("AB6")),
 165         Subsignal("clk_n", Pins("AB5")),
 166         Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
 167         Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
 168         Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6")),
 169         Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5"))
 170     ),
 171
 172     ("pcie_x8", 0,
 173         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 174         Subsignal("clk_p", Pins("AB6")),
 175         Subsignal("clk_n", Pins("AB5")),
 176         Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
 177         Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
 178         Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
 179         Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
 180     ),
 181
 182     ("sgmii_clock", 0,
 183         Subsignal("p", Pins("P26"), IOStandard("LVDS_25")),
 184         Subsignal("n", Pins("N26"), IOStandard("LVDS_25"))
 185     ),
 186
 187
 188     ("user_sma_mgt_refclk", 0,
 189         Subsignal("p", Pins("V6")),
 190         Subsignal("n", Pins("V5"))
 191     ),
 192     ("user_sma_mgt_tx", 0,
 193         Subsignal("p", Pins("R4")),
 194         Subsignal("n", Pins("R3"))
 195     ),
 196     ("user_sma_mgt_rx", 0,
 197         Subsignal("p", Pins("P2")),
 198         Subsignal("n", Pins("P1"))
 199     ),
 200
 201     ("sfp", 0,
 202         Subsignal("txp", Pins("U4")),
 203         Subsignal("txn", Pins("U3")),
 204         Subsignal("rxp", Pins("T2")),
 205         Subsignal("rxn", Pins("T1"))
 206     ),
 207     ("sfp_tx", 0,
 208         Subsignal("p", Pins("U4")),
 209         Subsignal("n", Pins("U3")),
 210     ),
 211     ("sfp_rx", 0,
 212         Subsignal("p", Pins("T2")),
 213         Subsignal("n", Pins("T1")),
 214     ),
 215     ("sfp_tx_disable_n", 0, Pins("AL8"), IOStandard("LVCMOS18")),
 216
 217     ("sfp", 1,
 218         Subsignal("txp", Pins("W4")),
 219         Subsignal("txn", Pins("W3")),
 220         Subsignal("rxp", Pins("V2")),
 221         Subsignal("rxn", Pins("V1"))
 222     ),
 223     ("sfp_tx", 1,
 224         Subsignal("p", Pins("W4")),
 225         Subsignal("n", Pins("W3")),
 226     ),
 227     ("sfp_rx", 1,
 228         Subsignal("p", Pins("V2")),
 229         Subsignal("n", Pins("V1")),
 230     ),
 231     ("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
 232 ]
 233
 234 _connectors = [
 235     ("HPC", {
 236         "DP0_C2M_P": "F6",
 237         "DP0_C2M_N": "F5",
 238         "DP0_M2C_P": "E4",
 239         "DP0_M2C_N": "E3",
 240         "DP1_C2M_P": "D6",
 241         "DP1_C2M_N": "D5",
 242         "DP1_M2C_P": "D2",
 243         "DP1_M2C_N": "D1",
 244         "DP2_C2M_P": "C4",
 245         "DP2_C2M_N": "C3",
 246         "DP2_M2C_P": "B2",
 247         "DP2_M2C_N": "B1",
 248         "DP3_C2M_P": "B6",
 249         "DP3_C2M_N": "B5",
 250         "DP3_M2C_P": "A4",
 251         "DP3_M2C_N": "A3",
 252         "DP4_C2M_P": "N4",
 253         "DP4_C2M_N": "N3",
 254         "DP4_M2C_P": "M2",
 255         "DP4_M2C_N": "M1",
 256         "DP5_C2M_P": "J4",
 257         "DP5_C2M_N": "J3",
 258         "DP5_M2C_P": "H2",
 259         "DP5_M2C_N": "H1",
 260         "DP6_C2M_P": "L4",
 261         "DP6_C2M_N": "L3",
 262         "DP6_M2C_P": "K2",
 263         "DP6_M2C_N": "K1",
 264         "DP7_C2M_P": "G4",
 265         "DP7_C2M_N": "G3",
 266         "DP7_M2C_P": "F2",
 267         "DP7_M2C_N": "F1",
 268         "LA06_P": "D13",
 269         "LA06_N": "C13",
 270         "LA10_P": "L8",
 271         "LA10_N": "K8",
 272         "LA14_P": "B10",
 273         "LA14_N": "A10",
 274         "LA18_CC_P": "E22",
 275         "LA18_CC_N": "E23",
 276         "LA27_P": "H21",
 277         "LA27_N": "G21",
 278         "HA01_CC_P": "E16",
 279         "HA01_CC_N": "D16",
 280         "HA05_P": "J15",
 281         "HA05_N": "J14",
 282         "HA09_P": "F18",
 283         "HA09_N": "F17",
 284         "HA13_P": "B14",
 285         "HA13_N": "A14",
 286         "HA16_P": "A19",
 287         "HA16_N": "A18",
 288         "HA20_P": "C19",
 289         "HA20_N": "B19",
 290         "CLK1_M2C_P": "E25",
 291         "CLK1_M2C_N": "D25",
 292         "LA00_CC_P": "H11",
 293         "LA00_CC_N": "G11",
 294         "LA03_P": "A13",
 295         "LA03_N": "A12",
 296         "LA08_P": "J8",
 297         "LA08_N": "H8",
 298         "LA12_P": "E10",
 299         "LA12_N": "D10",
 300         "LA16_P": "B9",
 301         "LA16_N": "A9",
 302         "LA20_P": "B24",
 303         "LA20_N": "A24",
 304         "LA22_P": "G24",
 305         "LA22_N": "F25",
 306         "LA25_P": "D20",
 307         "LA25_N": "D21",
 308         "LA29_P": "B20",
 309         "LA29_N": "A20",
 310         "LA31_P": "B25",
 311         "LA31_N": "A25",
 312         "LA33_P": "A27",
 313         "LA33_N": "A28",
 314         "HA03_P": "G15",
 315         "HA03_N": "G14",
 316         "HA07_P": "L19",
 317         "HA07_N": "L18",
 318         "HA11_P": "J19",
 319         "HA11_N": "J18",
 320         "HA14_P": "F15",
 321         "HA14_N": "F14",
 322         "HA18_P": "B17",
 323         "HA18_N": "B16",
 324         "HA22_P": "C18",
 325         "HA22_N": "C17",
 326         "GBTCLK1_M2C_P": "H6",
 327         "GBTCLK1_M2C_N": "H5",
 328         "GBTCLK0_M2C_P": "K6",
 329         "GBTCLK0_M2C_N": "K5",
 330         "LA01_CC_P": "G9",
 331         "LA01_CC_N": "F9",
 332         "LA05_P": "L13",
 333         "LA05_N": "K13",
 334         "LA09_P": "J9",
 335         "LA09_N": "H9",
 336         "LA13_P": "D9",
 337         "LA13_N": "C9",
 338         "LA17_CC_P": "D24",
 339         "LA17_CC_N": "C24",
 340         "LA23_P": "G22",
 341         "LA23_N": "F22",
 342         "LA26_P": "G20",
 343         "LA26_N": "F20",
 344         "PG_M2C": "L27",
 345         "HA00_CC_P": "G17",
 346         "HA00_CC_N": "G16",
 347         "HA04_P": "G19",
 348         "HA04_N": "F19",
 349         "HA08_P": "K18",
 350         "HA08_N": "K17",
 351         "HA12_P": "K16",
 352         "HA12_N": "J16",
 353         "HA15_P": "D14",
 354         "HA15_N": "C14",
 355         "HA19_P": "D19",
 356         "HA19_N": "D18",
 357         "PRSNT_M2C_B": "H24",
 358         "CLK0_M2C_P": "H12",
 359         "CLK0_M2C_N": "G12",
 360         "LA02_P": "K10",
 361         "LA02_N": "J10",
 362         "LA04_P": "L12",
 363         "LA04_N": "K12",
 364         "LA07_P": "F8",
 365         "LA07_N": "E8",
 366         "LA11_P": "K11",
 367         "LA11_N": "J11",
 368         "LA15_P": "D8",
 369         "LA15_N": "C8",
 370         "LA19_P": "C21",
 371         "LA19_N": "C22",
 372         "LA21_P": "F23",
 373         "LA21_N": "F24",
 374         "LA24_P": "E20",
 375         "LA24_N": "E21",
 376         "LA28_P": "B21",
 377         "LA28_N": "B22",
 378         "LA30_P": "C26",
 379         "LA30_N": "B26",
 380         "LA32_P": "E26",
 381         "LA32_N": "D26",
 382         "HA02_P": "H19",
 383         "HA02_N": "H18",
 384         "HA06_P": "L15",
 385         "HA06_N": "K15",
 386         "HA10_P": "H17",
 387         "HA10_N": "H16",
 388         "HA17_CC_P": "E18",
 389         "HA17_CC_N": "E17",
 390         "HA21_P": "E15",
 391         "HA21_N": "D15",
 392         "HA23_P": "B15",
 393         "HA23_N": "A15",
 394         }
 395     ),
 396     ("LPC", {
 397         "GBTCLK0_M2C_P": "AA24",
 398         "GBTCLK0_M2C_N": "AA25",
 399         "LA01_CC_P": "W25",
 400         "LA01_CC_N": "Y25",
 401         "LA05_P": "V27",
 402         "LA05_N": "V28",
 403         "LA09_P": "V26",
 404         "LA09_N": "W26",
 405         "LA13_P": "AA20",
 406         "LA13_N": "AB20",
 407         "LA17_CC_P": "AA32",
 408         "LA17_CC_N": "AB32",
 409         "LA23_P": "AD30",
 410         "LA23_N": "AD31",
 411         "LA26_P": "AF33",
 412         "LA26_N": "AG34",
 413         "CLK0_M2C_P": "AA24",
 414         "CLK0_M2C_N": "AA25",
 415         "LA02_P": "AA22",
 416         "LA02_N": "AB22",
 417         "LA04_P": "U26",
 418         "LA04_N": "U27",
 419         "LA07_P": "V22",
 420         "LA07_N": "V23",
 421         "LA11_P": "V21",
 422         "LA11_N": "W21",
 423         "LA15_P": "AB25",
 424         "LA15_N": "AB26",
 425         "LA19_P": "AA29",
 426         "LA19_N": "AB29",
 427         "LA21_P": "AC33",
 428         "LA21_N": "AD33",
 429         "LA24_P": "AE32",
 430         "LA24_N": "AF32",
 431         "LA28_P": "V31",
 432         "LA28_N": "W31",
 433         "LA30_P": "Y31",
 434         "LA30_N": "Y32",
 435         "LA32_P": "W30",
 436         "LA32_N": "Y30",
 437         "LA06_P": "V29",
 438         "LA06_N": "W29",
 439         "LA10_P": "T22",
 440         "LA10_N": "T23",
 441         "LA14_P": "U21",
 442         "LA14_N": "U22",
 443         "LA18_CC_P": "AB30",
 444         "LA18_CC_N": "AB31",
 445         "LA27_P": "AG31",
 446         "LA27_N": "AG32",
 447         "CLK1_M2C_P": "AC31",
 448         "CLK1_M2C_N": "AC32",
 449         "LA00_CC_P": "W23",
 450         "LA00_CC_N": "W24",
 451         "LA03_P": "W28",
 452         "LA03_N": "Y28",
 453         "LA08_P": "U24",
 454         "LA08_N": "U25",
 455         "LA12_P": "AC22",
 456         "LA12_N": "AC23",
 457         "LA16_P": "AB21",
 458         "LA16_N": "AC21",
 459         "LA20_P": "AA34",
 460         "LA20_N": "AB34",
 461         "LA22_P": "AC34",
 462         "LA22_N": "AD34",
 463         "LA25_P": "AE33",
 464         "LA25_N": "AF34",
 465         "LA29_P": "U34",
 466         "LA29_N": "V34",
 467         "LA31_P": "V33",
 468         "LA31_N": "W34",
 469         "LA33_P": "W33",
 470         "LA33_N": "Y33",
 471         }
 472     )
 473 ]
 474
 475
 476 class Platform(XilinxPlatform):
 477     default_clk_name = "clk125"
 478     default_clk_period = 8.0
 479
 480     def __init__(self):
 481         XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors,
 482             toolchain="vivado")
 483
 484     def create_programmer(self):
 485         return VivadoProgrammer()