litex/boards/platforms/kcu105.py

   1 from litex.build.generic_platform import *
   2 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
   3
   4
   5 _io = [
   6     ("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
   7     ("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
   8     ("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
   9     ("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
  10     ("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
  11     ("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
  12     ("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
  13     ("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
  14
  15     ("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
  16
  17     ("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
  18     ("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
  19     ("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
  20     ("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
  21     ("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
  22
  23     ("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
  24     ("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
  25     ("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
  26     ("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
  27
  28     ("user_sma_clock", 0,
  29         Subsignal("p", Pins("D23"), IOStandard("LVDS")),
  30         Subsignal("n", Pins("C23"), IOStandard("LVDS"))
  31     ),
  32     ("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
  33     ("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
  34
  35     ("clk125", 0,
  36         Subsignal("p", Pins("G10"), IOStandard("LVDS")),
  37         Subsignal("n", Pins("F10"), IOStandard("LVDS"))
  38     ),
  39
  40     ("clk300", 0,
  41         Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
  42         Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
  43     ),
  44
  45     ("i2c", 0,
  46         Subsignal("scl", Pins("J24")),
  47         Subsignal("sda", Pins("J25")),
  48         IOStandard("LVCMOS18")
  49     ),
  50
  51     ("serial", 0,
  52         Subsignal("cts", Pins("L23")),
  53         Subsignal("rts", Pins("K27")),
  54         Subsignal("tx", Pins("K26")),
  55         Subsignal("rx", Pins("G25")),
  56         IOStandard("LVCMOS18")
  57         ),
  58
  59     ("spiflash", 0,  # clock needs to be accessed through primitive
  60         Subsignal("cs_n", Pins("U7")),
  61         Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
  62         IOStandard("LVCMOS18")
  63     ),
  64
  65     ("spiflash", 1,  # clock needs to be accessed through primitive
  66         Subsignal("cs_n", Pins("G26")),
  67         Subsignal("dq", Pins("M20 L20 R21 R22")),
  68         IOStandard("LVCMOS18")
  69     ),
  70
  71     ("rotary", 0,
  72         Subsignal("a", Pins("Y21")),
  73         Subsignal("b", Pins("AD26")),
  74         Subsignal("push", Pins("AF28")),
  75         IOStandard("LVCMOS18")
  76     ),
  77
  78     ("hdmi", 0,
  79         Subsignal("d", Pins(
  80             "AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
  81             "AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
  82             "AG10 AK8")),
  83         Subsignal("de", Pins("AE11")),
  84         Subsignal("clk", Pins("AF13")),
  85         Subsignal("vsync", Pins("AH13")),
  86         Subsignal("hsync", Pins("AE13")),
  87         Subsignal("spdif", Pins("AE12")),
  88         Subsignal("spdif_out", Pins("AF12")),
  89         IOStandard("LVCMOS18")
  90     ),
  91
  92     ("pcie_x1", 0,
  93         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
  94         Subsignal("clk_p", Pins("AB6")),
  95         Subsignal("clk_n", Pins("AB5")),
  96         Subsignal("rx_p", Pins("AB2")),
  97         Subsignal("rx_n", Pins("AB1")),
  98         Subsignal("tx_p", Pins("AC3")),
  99         Subsignal("tx_n", Pins("AC4"))
 100     ),
 101
 102     ("pcie_x2", 0,
 103         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 104         Subsignal("clk_p", Pins("AB6")),
 105         Subsignal("clk_n", Pins("AB5")),
 106         Subsignal("rx_p", Pins("AB2 AD2")),
 107         Subsignal("rx_n", Pins("AB1 AD1")),
 108         Subsignal("tx_p", Pins("AC3 AE4")),
 109         Subsignal("tx_n", Pins("AC4 AE3"))
 110     ),
 111
 112     ("pcie_x4", 0,
 113         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 114         Subsignal("clk_p", Pins("AB6")),
 115         Subsignal("clk_n", Pins("AB5")),
 116         Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
 117         Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
 118         Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6")),
 119         Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5"))
 120     ),
 121
 122     ("pcie_x8", 0,
 123         Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
 124         Subsignal("clk_p", Pins("AB6")),
 125         Subsignal("clk_n", Pins("AB5")),
 126         Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
 127         Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
 128         Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
 129         Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
 130     ),
 131 ]
 132
 133 _connectors = [
 134     ("HPC", {
 135         "DP0_C2M_P": "F6",
 136         "DP0_C2M_N": "F5",
 137         "DP0_M2C_P": "E4",
 138         "DP0_M2C_N": "E3",
 139         "DP1_C2M_P": "D6",
 140         "DP1_C2M_N": "D5",
 141         "DP1_M2C_P": "D2",
 142         "DP1_M2C_N": "D1",
 143         "DP2_C2M_P": "C4",
 144         "DP2_C2M_N": "C3",
 145         "DP2_M2C_P": "B2",
 146         "DP2_M2C_N": "B1",
 147         "DP3_C2M_P": "B6",
 148         "DP3_C2M_N": "B5",
 149         "DP3_M2C_P": "A4",
 150         "DP3_M2C_N": "A3",
 151         "DP4_C2M_P": "N4",
 152         "DP4_C2M_N": "N3",
 153         "DP4_M2C_P": "M2",
 154         "DP4_M2C_N": "M1",
 155         "DP5_C2M_P": "J4",
 156         "DP5_C2M_N": "J3",
 157         "DP5_M2C_P": "H2",
 158         "DP5_M2C_N": "H1",
 159         "DP6_C2M_P": "L4",
 160         "DP6_C2M_N": "L3",
 161         "DP6_M2C_P": "K2",
 162         "DP6_M2C_N": "K1",
 163         "DP7_C2M_P": "G4",
 164         "DP7_C2M_N": "G3",
 165         "DP7_M2C_P": "F2",
 166         "DP7_M2C_N": "F1",
 167         "LA06_P": "D13",
 168         "LA06_N": "C13",
 169         "LA10_P": "L8",
 170         "LA10_N": "K8",
 171         "LA14_P": "B10",
 172         "LA14_N": "A10",
 173         "LA18_CC_P": "E22",
 174         "LA18_CC_N": "E23",
 175         "LA27_P": "H21",
 176         "LA27_N": "G21",
 177         "HA01_CC_P": "E16",
 178         "HA01_CC_N": "D16",
 179         "HA05_P": "J15",
 180         "HA05_N": "J14",
 181         "HA09_P": "F18",
 182         "HA09_N": "F17",
 183         "HA13_P": "B14",
 184         "HA13_N": "A14",
 185         "HA16_P": "A19",
 186         "HA16_N": "A18",
 187         "HA20_P": "C19",
 188         "HA20_N": "B19",
 189         "CLK1_M2C_P": "E25",
 190         "CLK1_M2C_N": "D25",
 191         "LA00_CC_P": "H11",
 192         "LA00_CC_N": "G11",
 193         "LA03_P": "A13",
 194         "LA03_N": "A12",
 195         "LA08_P": "J8",
 196         "LA08_N": "H8",
 197         "LA12_P": "E10",
 198         "LA12_N": "D10",
 199         "LA16_P": "B9",
 200         "LA16_N": "A9",
 201         "LA20_P": "B24",
 202         "LA20_N": "A24",
 203         "LA22_P": "G24",
 204         "LA22_N": "F25",
 205         "LA25_P": "D20",
 206         "LA25_N": "D21",
 207         "LA29_P": "B20",
 208         "LA29_N": "A20",
 209         "LA31_P": "B25",
 210         "LA31_N": "A25",
 211         "LA33_P": "A27",
 212         "LA33_N": "A28",
 213         "HA03_P": "G15",
 214         "HA03_N": "G14",
 215         "HA07_P": "L19",
 216         "HA07_N": "L18",
 217         "HA11_P": "J19",
 218         "HA11_N": "J18",
 219         "HA14_P": "F15",
 220         "HA14_N": "F14",
 221         "HA18_P": "B17",
 222         "HA18_N": "B16",
 223         "HA22_P": "C18",
 224         "HA22_N": "C17",
 225         "GBTCLK1_M2C_P": "H6",
 226         "GBTCLK1_M2C_N": "H5",
 227         "GBTCLK0_M2C_P": "K6",
 228         "GBTCLK0_M2C_N": "K5",
 229         "LA01_CC_P": "G9",
 230         "LA01_CC_N": "F9",
 231         "LA05_P": "L13",
 232         "LA05_N": "K13",
 233         "LA09_P": "J9",
 234         "LA09_N": "H9",
 235         "LA13_P": "D9",
 236         "LA13_N": "C9",
 237         "LA17_CC_P": "D24",
 238         "LA17_CC_N": "C24",
 239         "LA23_P": "G22",
 240         "LA23_N": "F22",
 241         "LA26_P": "G20",
 242         "LA26_N": "F20",
 243         "PG_M2C": "L27",
 244         "HA00_CC_P": "G17",
 245         "HA00_CC_N": "G16",
 246         "HA04_P": "G19",
 247         "HA04_N": "F19",
 248         "HA08_P": "K18",
 249         "HA08_N": "K17",
 250         "HA12_P": "K16",
 251         "HA12_N": "J16",
 252         "HA15_P": "D14",
 253         "HA15_N": "C14",
 254         "HA19_P": "D19",
 255         "HA19_N": "D18",
 256         "PRSNT_M2C_B": "H24",
 257         "CLK0_M2C_P": "H12",
 258         "CLK0_M2C_N": "G12",
 259         "LA02_P": "K10",
 260         "LA02_N": "J10",
 261         "LA04_P": "L12",
 262         "LA04_N": "K12",
 263         "LA07_P": "F8",
 264         "LA07_N": "E8",
 265         "LA11_P": "K11",
 266         "LA11_N": "J11",
 267         "LA15_P": "D8",
 268         "LA15_N": "C8",
 269         "LA19_P": "C21",
 270         "LA19_N": "C22",
 271         "LA21_P": "F23",
 272         "LA21_N": "F24",
 273         "LA24_P": "E20",
 274         "LA24_N": "E21",
 275         "LA28_P": "B21",
 276         "LA28_N": "B22",
 277         "LA30_P": "C26",
 278         "LA30_N": "B26",
 279         "LA32_P": "E26",
 280         "LA32_N": "D26",
 281         "HA02_P": "H19",
 282         "HA02_N": "H18",
 283         "HA06_P": "L15",
 284         "HA06_N": "K15",
 285         "HA10_P": "H17",
 286         "HA10_N": "H16",
 287         "HA17_CC_P": "E18",
 288         "HA17_CC_N": "E17",
 289         "HA21_P": "E15",
 290         "HA21_N": "D15",
 291         "HA23_P": "B15",
 292         "HA23_N": "A15",
 293         }
 294     ),
 295     ("LPC", {
 296         "GBTCLK0_M2C_P": "AA24",
 297         "GBTCLK0_M2C_N": "AA25",
 298         "LA01_CC_P": "W25",
 299         "LA01_CC_N": "Y25",
 300         "LA05_P": "V27",
 301         "LA05_N": "V28",
 302         "LA09_P": "V26",
 303         "LA09_N": "W26",
 304         "LA13_P": "AA20",
 305         "LA13_N": "AB20",
 306         "LA17_CC_P": "AA32",
 307         "LA17_CC_N": "AB32",
 308         "LA23_P": "AD30",
 309         "LA23_N": "AD31",
 310         "LA26_P": "AF33",
 311         "LA26_N": "AG34",
 312         "CLK0_M2C_P": "AA24",
 313         "CLK0_M2C_N": "AA25",
 314         "LA02_P": "AA22",
 315         "LA02_N": "AB22",
 316         "LA04_P": "U26",
 317         "LA04_N": "U27",
 318         "LA07_P": "V22",
 319         "LA07_N": "V23",
 320         "LA11_P": "V21",
 321         "LA11_N": "W21",
 322         "LA15_P": "AB25",
 323         "LA15_N": "AB26",
 324         "LA19_P": "AA29",
 325         "LA19_N": "AB29",
 326         "LA21_P": "AC33",
 327         "LA21_N": "AD33",
 328         "LA24_P": "AE32",
 329         "LA24_N": "AF32",
 330         "LA28_P": "V31",
 331         "LA28_N": "W31",
 332         "LA30_P": "Y31",
 333         "LA30_N": "Y32",
 334         "LA32_P": "W30",
 335         "LA32_N": "Y30",
 336         "LA06_P": "V29",
 337         "LA06_N": "W29",
 338         "LA10_P": "T22",
 339         "LA10_N": "T23",
 340         "LA14_P": "U21",
 341         "LA14_N": "U22",
 342         "LA18_CC_P": "AB30",
 343         "LA18_CC_N": "AB31",
 344         "LA27_P": "AG31",
 345         "LA27_N": "AG32",
 346         "CLK1_M2C_P": "AC31",
 347         "CLK1_M2C_N": "AC32",
 348         "LA00_CC_P": "W23",
 349         "LA00_CC_N": "W24",
 350         "LA03_P": "W28",
 351         "LA03_N": "Y28",
 352         "LA08_P": "U24",
 353         "LA08_N": "U25",
 354         "LA12_P": "AC22",
 355         "LA12_N": "AC23",
 356         "LA16_P": "AB21",
 357         "LA16_N": "AC21",
 358         "LA20_P": "AA34",
 359         "LA20_N": "AB34",
 360         "LA22_P": "AC34",
 361         "LA22_N": "AD34",
 362         "LA25_P": "AE33",
 363         "LA25_N": "AF34",
 364         "LA29_P": "U34",
 365         "LA29_N": "V34",
 366         "LA31_P": "V33",
 367         "LA31_N": "W34",
 368         "LA33_P": "W33",
 369         "LA33_N": "Y33",
 370         }
 371     )
 372 ]
 373
 374
 375 class Platform(XilinxPlatform):
 376     default_clk_name = "clk125"
 377     default_clk_period = 8.0
 378
 379     def __init__(self):
 380         XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors,
 381             toolchain="vivado")
 382
 383     def create_programmer(self):
 384         return VivadoProgrammer()